Develop Early, Test Faster, and Manage Better

I took the title for this blog post directly from the subhead of a Virtutech data sheet. Like Mentor’s Vista, which I blogged about yesterday, Virtutech is offering a system-simulation tool based on OSCI TLM 2.0. Virtutech’s product is called Simics (a contraction of “simulation of ICs”). I discussed Simics with Virtutech’s VP of Marketing Michel Genard at a table in a darkened Starbucks at the Marriott behind the Moscone Convention Center at DAC.

Genard emphasized two of the real advantages of system simulation: very fast exploration of a hardware design space and early software development on a functional virtual prototype. Simics provides hooks needed to allow both hardware and software developers to debug their systems at the same time.

Now that last bit should seem like a good thing, but it could also be a prescription for chaos depending on how the overall product-design project is run. For decades, many project teams have left the wall between hardware and software development (and between design and manufacturing for that matter) in place. Software teams often struggle with pre-designed hardware that can’t quite muster the performance needed in some critical code sections. Hardware teams struggle with the need to design systems from incomplete, high-level specifications long before any software is written. Consequently, some design teams have developed little or no experience in coordinating simultaneous hardware and software development. As I wrote, it’s a prescription for chaos.

Genard agreed with me and laid the responsibility for any chaos that occurs squarely on management. “Managers must take ownership and set a development strategy for the team,” he said. Management needs to lead design strategy, not just let it happen. However, said Genard, it seems that most management teams do not take action unless there’s a direct affect on manufacturing costs. Software development often appears to be “free” because the software is just bits to be poured into a ROM that’s already designed into the system BOM. However, as my good friend Jack Ganssle loves to say, Software or firmware is the most expensive thing in the universe. (“One of my mantras is that firmware is the most expensive thing in the universe. Though it has no weight, no real substance, the cost to create reliable, maintainable and documented code is astronomical.”)

I’m hopeful that this new crop of system-level simulation tools will cure a lot of design ills the way that HDLs cured the problem of trying to design ASICs with hundreds of thousands of gates using schematic-based design. That design tool proved inadequate to the task and HDL-based logic synthesis rapidly became the leading design technique for ASIC and then SOC design. That revolution occurred twenty years ago and we’ve not had another design revolution since then.

This revolution might just catch fire. SOC-design teams are already familiar with and use RTL and gate-level simulation. However, SOCs with many millions of gates are just too big and complex to fully simulate with lower-level simulators unless you have a 10-year development cycle. And who does? System-level simulation tools offer the hope of making SOC-level simulation not only a reality, but an obvious and brain-dead-easy choice. They also offer the promise of vastly improving early software development.

And we have to make this jump. Why? Genard summed it up well. “One billion gates. We don’t know how to do that. We have no clue as to how to do that affordably.”

Genard already sees system-level simulation tools slowly infusing into the design community. “It’s like going to the dentist,” he says. “You don’t go until you feel real pain. Without pain, most people won’t go to the dentist even for a free cleaning.” Design pain has not yet crossed the threshold where all design teams feel they must use system-level simulation. For now, there’s experimentation by some but no commitment by an industry.

Bring on the pain.