EDP 2009: Gary Smith on the State of EDA—Tumult and the Return of the ASIC Business

Everyone in EDA knows Gary Smith. He’s the industry’s foremost EDA analyst (garysmitheda.com); one of the organizers of the Electronic Design Processes Workshop that I attended this week; and he spoke this morning on the state of EDA. Unsurprisingly, he said the industry is in great tumult.

Gary separates the EDA customer base into four segments. The top two are the Power Users—who get every ounce of performance from the most advanced process nodes available—and the Upper Mainstream Users—who trail the Power Users by a process node or two. Generally, like any customer pyramid, there are more Upper Mainstream Users than Power Users and in 2001, the EDA companies got 41.9% of their revenue from the bigger base of Upper Mainstream Users. In 2002, the Power Users came to the fore. That means that the number of seats in the main EDA revenue segment shrank, which puts the EDA companies in a more precarious position. The latest news from the EDA industry seems to confirm this position.

It’s very expensive to be an EDA Power User. It’s hard too. You must take on the responsibility of physical design and below 65nm, that’s a pretty daunting task. (Unlike many journalists who overuse the term all over the place, I rarely use the word “daunting” but I do feel it is truly appropriate here.) At 22nm, the patterns to be written look more like blobs than IC masks and there are hundreds of patterning rules that must be followed to get any sort of yield. So the effort involved discourages many from becoming Power Users unless they really need to do so. In fact, the forcing function is away from custom chips and towards FPGAs, which is one reason that the FPGA companies like to say that there are 30x more FPGA design starts than ASIC/SOC design starts. Only those projects that must have the benefits of faster speeds, higher densities/lower unit costs, and lower operating power contemplate the design of an SOC.

Despite this assessment, which looks bad for EDA on the surface, Smith forecasts a revival of the ASIC industry although he says that he doesn’t know what form it will take. Back in the 1980s, during the heyday of the gate array, ASIC vendors like LSI Logic and VLSI Technology took logical ASIC designs from customers and did the physical design for them. That model allowed customers to stay in the nice, clean world of Boolean algebra and left it to the ASIC vendors to deal with the messy, analog world of real-world silicon.

The industry got away from that model because the EDA tool vendors were able to encapsulate a lot of the required silicon knowledge and expertise into their tools, which allowed more companies to tackle the physical design issues themselves simply by buying and using the right EDA tools. Chip physics were so much simpler back then. Now, they’re not. That change provides an opportunity for new-world ASIC vendors to appear, including vendors such as eASIC and eSilicon that have already appeared. Smith predicts that the resurgence of the ASIC-design model will take 3 to 5 years, but seems certain that it will happen. “Probably closer to 3 years than 5,” he says.