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Ten Things You Want to be Sure to put into Your SOC

February 23, 2010

I’ve just spent the day at DVcon in San Jose and met a friend of mine, Gary Stringham, who consults on SOC and embedded systems design. He spent years designing laser printers around SOCs at HP and he’s learned a thing or two about the trials and tribulations of SOC design. Gary’s just published a book, Hardware/Firmware Interface Design: Best Practices for Improving Embedded Systems Development. Embedded within the book are 300 best practices. I also picked up a brochure from Gary’s DVcon booth titled “Ten Hooks You’ll Wish You Had in Your Chip.” I like the brochure and the book. I can’t reproduce the book’s 300 best practices but I can give you the ten eminently practical things you’ll wish you’d put into your chip:

1.       Make address and counter registers firmware-readable.

2.       Provide a firmware-register that contains the current state of each state machine.

3.       Provide read access to many signals internal to the chip through a register.

4.       Provide read access to the current state of key input and output signal pins through a register.

5.       Provide non-destructive read access to internal memory including FIFOs and buffers. Also include read access to memory management registers and to the counters used for head and tail pointers.

6.       Provide a register with control bits connected to the power-on resets for each block on the chip.

7.       Provide a separate test and debug interrupt module that will generate interrupts from different internal signals.

8.       Provide means within a block to simulate external signals, which may be as simple as setting a bit or by enabling a signal pattern generator.

9.       Provide points in the middle of a pipeline where firmware can pull data out of or put data into a pipeline.

10.   For countdown timers that reload and then continue counting when an event occurs, save a copy of the timer value just prior to the event in a separate register that’s firmware readable.

Perhaps Gary’s approach sounds like the kind of help you’d like on your next (or current) SOC design project. Check out his free newsletter: http://garystringham.com/newsletter.shtml.

 

Posted by Steve Leibson on February 23, 2010 | Comments (5)

February 28, 2010
In response to: Ten Things You Want to be Sure to put into Your SOC
Gary Stringham commented:

@Monte Yes, registers are not always sufficient, but these are tools in the debugging toolbox like logic analyzers and JTAG access. @Standard JTAG access is one debugging tool but there are times when it won't work, such as when the whole product is buttoned up and the system is running something that can't be halted. The above hooks are intended to be used by firmware (embedded software) to aid and troublshoot integration with hardware.


February 26, 2010
In response to: Ten Things You Want to be Sure to put into Your SOC
Standard bearer commented:

Hmm no mention of JTAG access. What with TI and Freescale trumpeting the new IEEE 1149.7 SOC test and debug standard I thought that might top of the list ?!


February 25, 2010
In response to: Ten Things You Want to be Sure to put into Your SOC
Andy Neil commented:

A past Client's technical manager always used to say, "if you don't have enough system resources to allocate 10% for diagnostics, then you don't have enough system resources". He said that in the context of embedded firmware; but I think it applies as much to hardware - and, in fact, the whole system. Andy Neil Technical Director Antronics Ltd.


February 24, 2010
In response to: Ten Things You Want to be Sure to put into Your SOC
philip casini commented:

Steve, I think this piece is right on target. Many of the points on your wish list are available through an new SoC System Managemnt subsystem IP called SSM. This IP was launched in October at the GSA Expo and much has been written on it in various blogs. It is currently sold through the www.chip-start.com channel. The product defintion and archiecture was developed by Advance Tech Marketing. Perhaps if you feel this topic is worth while to do a follow up on we can dialogue about SSM. Phil Casini Managing Partner Advance Tech Marketing


February 24, 2010
In response to: Ten Things You Want to be Sure to put into Your SOC
Monte Dalrymple commented:

My last design had a large embedded DRAM. I added a test mode that brought out the address and data bus for the DRAM. This test mode is how we found that the memory was changing the output data on the wrong edge of the clock... which would have been essentially impossible to deduce without the logic analyzer trace while in this test mode. Sometimes just registering things for firmware access isn't enough.

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