Free EDN Webcast: Low-Power SOC Design

Need to design SOCs that maximize performance for every microJoule? I’ll be conducting a free Web seminar next week (Wednesday, July 18) on the topic of configured microprocessor cores that help accomplish this objective by greatly reducing the number of cycles needed to execute a task without the need to use manually coded RTL hardware blocks or assembly-language programming. I’ll be explaining these concepts in depth by exploring the abilities of configurable processors and through three specific, detailed task examples (AES encryption, Viterbi decoding, and FFTs) that benefit from this design approach.

Key points you’ll learn:

• Configured processor cores can reduce task energy consumption by more than 10x
• Many types of tasks can be accelerated using processor configuration
• Configured processor cores reduce manual RTL coding and verification in low-power applications
• Buses are not the ideal choice for low-power, on-chip interblock communications

Register here.