The Name’s Bond, Carbon Bond: Graphene FETs and Moore’s Law Scaling

Yesterday, my inner device physicist got carried away thinking about the possibilities of nanometer-scale graphene FETs. Today, my inner system designer started asking hard questions. The first question was one of scaling. If silicon scaling ends with low-nanometer feature size and room-temp graphene FETs take over at 2 nm, then how many generations do I get before graphene scaling ends?

To figure that out, I look at the picture from yesterday’s blogs, which essentially shows a FET channel made from a quantum wire that’s essentially a linear assembly of carbon hexagonal rings. So to figure out how wide that quantum wire is, you need to know the carbon-carbon bond length for graphene. Turns out, the carbon-carbon bond length is 1.42 Angstroms or 0.142 nm. So the channel width of that minimal quantum wire is around 2.4 Angstroms or 0.24 nm. That gives a bit less than 10x linear scaling room or about ten Moore’s-Law generations—assuming a 0.7x scale factor per generation—or three Moore’s-Law generations—assuming a 0.5x scale factor per generation. So graphene-based IC fabrication might extend physical lithographic scaling by about six to 20 years, assuming we can figure out how to pattern Angstrom-scale features.

Next, I wonder about building logic systems based on graphene FETs. It looks to me as though graphene FETs are depletion mode FETs. With no gate bias, the FET conducts. Negative gate bias cuts the electron flow. This is like depletion-mode IGFETs. I don’t see a way to create enhancement-mode graphene FETs when the graphene already conducts so well and we’re not using impurities to alter channel conductivity. So for system design, we’d have to return to the days when we had only one type of transistor for logic circuits (The PMOS and NMOS days of the 1970s, before CMOS rose in popularity). Certainly possible, but disruptive to the way we design today.

Finally, I thought about what happens when we get to the limits of 2D scaling. Might this finally drive us to 3D chip fabrication? At first blush, it seems that the 2D graphene circuitry might lend itself well to 3D fabrication scaling far better than essentially 3D planar structures of today’s silicon. It’ll all depend on our ability to create high-quality monoatomic layers.

All exciting questions for the future, I think.