Altera Licenses MIPS32 Processor Architecture

October 6, 2009

Even though it’s an obvious technological slam dunk, the fusion of FPGA fabrics with microprocessor architectures on one slab of silicon has a checkered history. Often it seems, either the wrong processor architecture ended up on the silicon or the grafting of the FPGA fabric to the processor’s buses seemingly failed to knit properly. In any case, FPGAs with on-chip hard IP processor cores have not set the world on fire. In addition, although FPGA fabrics can be used to implement soft-IP processors, the result is a lot like trying to teach a pig to sing. The synthesized processors run very slowly, primarily because of the extreme routing congestion around the processor’s register file. The hand-optimized processor cores offered by the major FPGA players are useful and faster, but they’re not especially powerful. Microprocessor cores are about four times faster when implemented as hard cores on the FPGA’s silicon. Consequently, the on-and-off marriage of processors and FPGAs has therefore been somewhat quiet for a while. Until now.

MIPS Technologies announced today that Altera has licensed the MIPS32 RISC architecture. The announcement provides no further details and Altera’s site doesn’t say anything about this license yet. So we’re left to wonder, for now. Is this the time that an FPGA vendor will get it right?

Let’s hope so, because there is an obvious match between processors and FPGAs, much like the match between chocolate and peanut butter in Reese’s Peanut Butter Cups. The two just go together. However, there are some technological hurdles. First, the FPGA designers need to make some intelligent choices when wiring up the processor core to the FPGA fabric. Then there’s the not-so-trivial matter of code development and debugging support. JTAG emulation goes a long way towards making things right in this arena, but it does take some thinking that FPGA vendors aren’t necessarily accustomed to and it may require some expansion of the FPGA vendor’s ecosystem.

Finally, there’s the whole question of core quantity. A MIPS32 core is pretty small compared to an FPGA fabric. You can hide a passel of 32-bit RISC processors in the interstitial routing spaces of an FPGA. So how many processor cores is enough? One? Two? Four? Unicore, multicore, or manycore?

Expect many interesting things to come.

Note: Altera announced a license for the MIPS32 4K core nine years ago for the APEX FPGAs.

Posted by Steve Leibson on October 6, 2009 | Comments (6)

October 12, 2009

In response to: Altera Licenses MIPS32 Processor Architecture
Jonah Probell commented:

What does a MIPS core offer in FPGAs that Nios II doesn't? The clock speed would be similar, at best. Both have JTAG debug capability and MMU-based Linux support. The ISAs are similar and the difference irrelevant since few, if any, FPGA users write assembly code anyway. Surely those communications system designers could recompile their MIPS code for Nios II as they switch from ASICs to FPGAs. I can contemplate no compelling reason for Altera to offer a MIPS core. Since the switch within Altera would require significant work, I will go out on a limb and predict that Altera will never offer their own implementation of a MIPS core.

October 7, 2009

In response to: Altera Licenses MIPS32 Processor Architecture
Steve Leibson commented:

Thanks Anon. The article contains a lot of conjecture by analysts based on no new info. What Altera will do with the MIPS core is still up in the air. That's what I get from Dylan McGrath's article. Note: Altera is under no obligation to explain what it's doing.

October 7, 2009

In response to: Altera Licenses MIPS32 Processor Architecture
Anon commented:

I think you all should check out this article on EEtimes related to this announcement: www.eetimes.com/news/design/showArticle.jhtml?articleID=220301386

October 6, 2009

In response to: Altera Licenses MIPS32 Processor Architecture
Dave Jones commented:

If they follow through, can they at least put big silicon in low pin count usable packages please...

October 6, 2009

In response to: Altera Licenses MIPS32 Processor Architecture
Steve Leibson commented:

Jim, I agree with you that it's not worked out in the past. However, I cannot buy into your TV/DVD player analogy. By forcing processor signals to go off chip from the processor and then back on chip to the FPGA, you lose potential performance from both pin limitations on the number of connections and from impedance limitations on clock speed. In theory, you can get better performance if both the processor and FPGA fabric are on the same die. In practice, you need some real systems engineering to make the design work well. So far, theory and practice have not converged for processors and FPGAs on the same piece of silicon. Could still happen, however.

October 6, 2009

In response to: Altera Licenses MIPS32 Processor Architecture
Jim Turley commented:

This *seems* like a perfect match, but like celebrity marriages, it may break up shortly. Lots of systems include both a processor and an FPGA, so why not merge them together? The logic would seem irrefutable. Yet it never seems to quite work out. My theory is that it's like combining a TV set with a DVD player. An obvious match, right? Yet although many companies make such a beast, few customers ever buy one. I think that's because people like to make those decisions separately. I want *that* TV and *that* DVD player, and combining them means I don't get to choose the one I want. Similarly, I think engineers want to choose their CPU separately from their FPGA. Both are highly differentiated products with loyal followers. Combining the two only decreases, not increases, the attraction. Still, let's hope it works, for MIPS' and Altera's sake.

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