Grant Martin on ESL, Multicore SOCs, and SMP Systems

EDA über-editor Richard Goering recently interviewed my friend and colleague Grant Martin for his online EDA and design publication SCDsource. The topic was ESL (electronic system level) design tools and system-level SOC design. The interview is here (you need to register to read it). Grant spent 10 years in the office of the CTO at Cadence as a Cadence Fellow. It’s a real privilege to be able to talk to Grant regularly because he knows so much about design. Here are some particularly insightful comments extracted from his SCDsource interview:

On the success of ESL:

ESL is more successful than many people give it credit for, because many people take a narrow view of what ESL is. I divide it into four or five different areas. Some of those areas are widely used by system experts and algorithm and architecture experts. One such area is algorithmic modeling, where you can talk about a tool like SPW [CoWare Signal Processing Designer] that goes back to the 1980’s, or Cossap, which is now [Synopsys] System Studio, which has a heritage almost that long. And then of course there’s the big one in the room, which is Mathworks with Simulink. Many people don’t recognize these tools as being ESL, but they are very widely used.

On the use of ESL:

Some people say that a virtual platform is composed of fast functional models that are instruction accurate, but not cycle accurate. But another kind of virtual platform is derived from cycle-accurate architectural models. It runs much more slowly, but it’s still much faster than any RTL execution, and it can be used for detailed verification where timing aspects are very critical.

You can use these two kinds of virtual platforms in conjunction with each other. The cycle-accurate one is used by the team putting the architecture together, and the fast functional one is used by software people trying to functionally validate their software. But if there are critical real-time or timing-dependent issues in the system, software people will need access to the cycle-accurate platform as well. You need a suitable mix of both types of verification.

On the topic of convenient concurrency:

Convenient concurrency embraces asymmetric multiprocessing, which is often dataflow oriented. It uses the compositional mechanism of multiple subsystems handling different functions. In that sense you’re never really programming in parallel until you try to build the coordinator between the different subsystems.

On multicore SMP systems:

SMP can also be used in a way that avoids parallel programming. Let’s say I have a number of general-purpose tasks, and those tasks don’t interact all that much. At any particular point I may only be able to run a few of them – others may be waiting for data. What I want is the ability to move those tasks around.