NAND Read Disturb: Shoo Fly, Don’t Bother Me

Steve. I was assmuming that since the read disturb is essentially integrating stray electrons while the wired gates are enabled to the floating gates, that mirroring the read gate pluse with an equal negative gate pulse/period (the N-FETS will still remain off) should have equal probability of de-integrating stray electrons. Those floating gates more prone to gain electrons should be more prone to lose them. Similarly the more stable floating gates would have less probability of gaining or losing electrons. This would be similar to applying an AC signal through a charged capacitor. With a 50% duty cycle signal the original DC charge on the capacitor should remain unchanged. So as I see it, the information stored on the floating gate should dominate since the gate control voltage will be sum zero despite the number of read operations. (Naturally the gate voltage needs to be tri-state: +, -, 0) since the gate should be ideally kept at zero whenever the word/page is not being accessed, etc. I agree that tying all the gates together for read access is required to simplify access to the array, and so all of the floating gates will encounter the same read enable logic signals and thus the same read-disturb problem. But then my idea my contribute to wear more than ease the read disturb phenomenon. In Electronics my mechanical Engineer friends are often blown away when I tell them that we're building devices with over a Billion Transistors and they can't imagine a machine with anywhere near that many fasteners. Stanley

Stanley/Stiggle: I don't think you have voiced a dumb idea, but the reason that NAND Flash has this read disturb problem is because of the way many FETs are wired together, to minimize on-chip wiring and therefore real-estate consumption by that wiring. You're really talking about partially erasing what the read-disturb phenomena has written. NAND Flash has a block-erase approach to minimize wiring, so I think your idea would end up being worse than the disease in terms of chip economics. From what I've seen, the industry is looking towards NAND Flash management to deal with a raft of problems in NAND Flash devices including read disturb.

I recall working on an A/D convertor stage and found current injection issues from the gate lines. One way we corrected this was using a balancing gate pulse. It seems logical that a negative gate pulse could be introduced after each read to "subtract off" if you will, the stray electrons which accumulate and cause the phenomenon. Although it wouldn't really increase the complexity of the memory array, it will require a few changes to the gate logic and require a charge pump for the negative rail. Or is this just another one of my really stupid ideas? Regards, Stanley

Stiggle: Google also dredged up this communique. I don't know the source or the date, so take it for what it's worth: Recently our founder had lunch with a STMicro engineer that knew quite a bit about NAND and specifically the read-disturb failure modes. He told us that after 100,000 or so reads of a sector, the stored data is actually very likely to experience corruption. Subsequent reads of the sector will return the same corrupted data, but the flash sector can be erased and reprogrammed (with the same data or otherwise) for another 100,000 or so reads. Towards the end of the useable life of the flash, a written sector may only be good for 1000 (or less) reads before it looses value. He also reaffirmed that the quality of NAND chips have peaked and we should expect the NAND "quirks" to get worse in the future. When asked for market predictions on alternative NAND chips with embedded controller logic in the chip (such as OneNAND, etc..) STMicro seems to believe those chips will be confined to niche markets and the current architecture of the 2k sector NAND chip will be where all the volume will be. I'm not sure if YAFFS is currently pursuing support of OneNAND, but from the sound of it it may not be a big deal either way. Is it still the current behavior of YAFFS2 to retire a sector permanently that experiences a read-disturb? We still seem to have a return rate of our boards about 1 every couple months with YAFFS having marked a large proportion of the flash sectors bad. This is much worse than the failure rates we have seen for CompactFlash cards-- which are usign the same NAND chips inside as YAFFS. In every case we've done failure analysis, the flash is almost 100% good after wiping the flash clean and unmarking the sectors bad. //Jesse Off [Steve's Note: YAFFS is "Yet another Flash File System" and is available at www.yaffs.net]

Here's the "official" word on NAND Flash read disturb error from Ed Doller: With NAND there are many interrelated factors that contribute to the observable error rates. Among other things, read disturb is related to the number of cycles and the temperature at which those cycles were done. The degree of system level error correction also plays a part as does the lithography of the material as this phenomenon gets worse with cell scaling. To directly answer the question, though, 1000 reads is unlikely to be problematic, applications approaching 1M reads will likely have to take special measures to deal with this effect. Keep I mind that 1M reads is far more then any "data" application but can easily be achieved in a "code" application when paging is performed. I hope this helps. Ed

How many read pulses are we talking about to reach 1% bit changes?