Altera and The Great FPGA Story

I just returned from the Globalpress Summit in San Francisco. The keynote speaker on day one was John Daane, president, CEO, and Chairman of the Board at Altera, one of the two leading FPGA vendors as measured by market share. In his presentation, Daane told a great story.

FPGAs are truly remarkable and immensely valuable parts. They allow system designers to achieve very high integration levels without the need for or the expense and effort of designing an ASIC. Ever since the first PALs from MMI appeared in the early 1980s, programmable logic parts have grown in capability, performance, and popularity. You can now fit good-sized systems into an FPGA. Every year, FPGAs bite further into the soft underbelly of the ASIC market by taking on increasingly large system designs that formerly had to be implemented in an ASIC. (Every year, the ASIC’s reach also increases, but that’s a different story.) New diffused functions such as DSP function units and programmable, high-speed serial ports greatly expand the types of applications that can use FPGAs. In addition, FPGAs with reasonable gate capacity cost only a few dollars, so they can be remarkably handy when you need to patch an existing system (to add a feature or fix a bug). You can just tack an FPGA onto your existing ASIC or ASSP and get another generation from your existing board-level system design, sometimes with a relatively simple upgrade at relatively low cost. There’s absolutely no denying the utility of these parts.

Yes, it’s a great story. Too bad it’s not the one Daane told to the editors at Globalpress.

As noted by EDN’s Ron Wilson and Electronics Weekly’s David Manners, Daane’s story reaches considerably beyond the already big, rich world of the FPGA. Apparently, that world isn’t enough. As Wilson writes:

“Daane claimed that last year almost 90 percent of ASIC design starts were at nodes of 130 nm or above, while this year Altera has begun sampling 40 nm FPGAs. He used this to justify comparing the die size, performance, and power of a 40 nm FPGA against those of a 130 nm ASIC, and claimed that on this basis, FPGAs would be an alternative for 88 percent of ASIC design starts.”

Manners quotes Daane:

“ ‘We’re now at the tipping point when PLDs can replace the entire ASIC market,’ said Daane.”

Whoa, Nelly!

Now it’s absolutely true that FPGAs own an increasingly attractive position in the 3-dimensional design space of price, performance, and power for system implementations, but they don’t fill the entire system-on-chip design space just yet. That space actually expands (like our own universe) as ASIC lithographies continue to shrink. Daane’s assertion that 90% of ASIC design starts were at nodes of 130nm and above may be a convenient straw man for favorably comparing Altera’s 40nm FPGAs to 130nm ASICs, but the claim just doesn’t ring true based on our own ASIC-design customer and prospect contacts at Tensilica. It’s been quite a while since I’ve heard of anyone talking about using a 130nm process technology for an ASIC design. Most ASIC designs I hear about are planned for either 90nm or 65nm fabrication and—just to be certain—I confirmed that impression with my boss Steve Roddy, Tensilica’s Marketing VP, who knows about all of the designs we hear about.

A few hours after Daane’s keynote presentation, during an “FPGA versus ASIC” panel, Dr. Kurt Huang who is a Marketing Director at Global Unichip, a Taiwan ASIC design service, listed the process technologies his company is targeting with its designs. A graph in the company’s brochure shows that Global Unichip taped out more 90nm designs than 130 nm designs in 2008. That year, designs at 90nm and below outnumbered designs at 130nm and above at Global Unichip.

During the panel, Huang said that about 70% of the design contracts won during the first two months of 2009 are for designs based on 90nm lithographies or smaller and about 30% are for designs using geometries larger than 90nm. Now those figures jive a lot better with my own experience. The 130nm node may be the ASIC manufacturing volume leader at the moment, based on existing designs, but new ASIC designs largely target the newer process lithographies that deliver lower unit costs.

Towards the end of his keynote presentation, Daane said that Altera’s new 40nm Stratix IV FPGAs are enjoying the most rapid adoption of any FPGAs the company has ever introduced. I’m fully willing to believe that story.