The biggest challenge in EDA may be the business, not the technology

EDA used to drive Moore’s law. One of the overriding themes at DAC this year is that has somehow fallen behind the industry’s pace car, or at least the current iteration of it, replete with multiple cores and multiple power zones. There are more bugs, a higher rate of defects in the final chips, more chips missing deadlines and seemingly more problems to solve at every step.

Still, the progression of what needs to happen in EDA software is relatively well understood, even if it isn’t always perfectly executed and all the pieces aren’t fully automated. EDA is being called upon to solve some of the thorniest issues in physics, and it’s no surprise that not everything works perfectly all the time.

Less obvious, however, what’s happening on the business and business process side. This, after all, is the elite of engineering, and what’s top of mind for top engineers isn’t business-related. It’s solving interesting problems. The trouble is that business issues have quietly become an interesting challenge of their own. As complexity grows with each process node, the end of classical scaling has forced chip companies to begin looking more holistically at chips in order to achieve both performance gains and a reduction in power.

For more than a decade, classical scaling had allowed a concurrent increase in performance with each new process node. That came to a grinding halt at 90-nm, and chip companies have had to look elsewhere for their performance gains. The solution was to bring chip architects together with every step of the design process — in some cases even up to the end user device and the application software that runs on it — and all the way out to the manufacturing of the chips, to make sure the chips can be manufactured with reasonable yield.

The bridges built across the EDA world, however, have been far less robust. While there is talk about electronic-system level design, and a number of startups are working to develop higher-abstraction layer products in that space, a concurrent issue is that the chip design world has become more fragmented at a time when it needs to be less fragmented. The sheer complexity of building chips has forced companies into ecosystems and created the need for IP software and tools to integrate it. The chips also have to be tested, which helps explain the relatively new interest of companies like National Instruments and Agilent in the EDA space — and verified. And then they usually have to be respun to achieve the lower power, higher yield and better performance that new chips are supposed to provide.

While their customers are coming together to solve these issues, EDA companies are not. In the past, they have gotten around these kinds of deficiencies by simply gobbling up startups. Viewed over the past couple decades, the EDA model has largely resembled a roll-up strategy, where different pieces were cobbled together by buying up different companies. The problem this time is that there aren’t as many EDA startups because venture capitalists don’t see a clear exit strategy for their investments, and almost no one is getting funding to fill in the gaps of existing flows.

Chip manufacturers are complaining that EDA tools aren’t keeping up with their demands, but the deeper issue may be that EDA businesses aren’t keeping up with their customers’ changing business models. Technical problems can be solved by engineers. Business problems can be solved by businesspeople. Unfortunately, the two of those don’t often go together, and when they do it’s not always smoothly or by choice.