Paper looks at capacitance in power planes for high-speed signaling

Since its inception, DesignCon has been the pre-eminent conference for signal integrity and EMI issues. This year is no exception: I’m going to try to attend a paper with the intriguing title, ”Are power planes necessary for high-speed signaling?” on the morning of Thursday, Feb. 2.

From the paper abstract it looks like the authors will cover new techniques to juggle capacitance requirements through technologies like thin dielectrics, embedded capacitance, and high frequency decoupling capacitors.

Here’s the abstract: The performance of a system depends heavily on the communication speed between integrated circuits, which is constrained by the power delivery networks (PDNs). The disruption between the power & ground planes based on the low target impedance concept induces return path discontinuities during data transitions, which create displacement current sources between the power & ground planes. These sources induce excessive power supply noise which can only be reduced by increasing the capacitance requirements through new technologies such as thin dielectrics, embedded capacitance, high frequency decoupling capacitors etc. The new PDN design proposed here using power transmission lines (PTLs) enables both power & signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed. Extensive simulations and measurements are shown using the PTL approach to demonstrate the enhanced signal integrity as compared to the currently practiced approaches.

The lead author is Suzanne Huh, an engineer at Intel who’s pursuing her PhD at Georgia Tech. You can register for the 4-day conference, January 30-Feb 2 at the Santa Clara Convention Center here. (The free Expo is Jan. 31- Feb 1; You can reserve your free Expo pass here.)