LSI builds on its networking multicore SoC portfolio

Wilson’s simplified guide to SoC design states that there are only two major tasks in modern SoC design: picking the IP blocks, and putting them together. The same can be said, apparently, about managing a line of networking products. At least that appears to be the message behind a set of introductions from LSI this morning. The company rolled out two communications processor SoCs and one Tarari content processor. All these chips are rooted in the notion of starting with a rich portfolio of functional IP blocks and then integrating them based on the data flow in a particular application.

The two communications processors make an interesting contrast. They are similar in composition, both being assemblies of pre-developed processing and I/O elements. But they represent two different ways of thinking about packet processing, coming, one suspects, from two different LSI customers. The first chip seems to anticipate the merger of the control and data planes, making no specific provision for a control-plane processor except for the ability to attach an external Intel Xeon. Instead, the data plane is populated with powerful embedded CPUs that can handle control tasks as part of their task mix. The second, chip, in contrast, makes an explicit distinction between control and data planes.

The first chip, an Axxia packet processor, switch, and buffer, emphasizes general-purpose computing power with the support of only a couple of hardware accelerators. The chip, done in IBM’s 45nm SoI embedded-DRAM process, unleashes four PowerPC 476 CPUs–each running at up to 1.8 GHz and each armed with half a megabyte of L2 cache-on the packet stream. The PowerPCs are supported by deep-packet-inspection, security, and classification engines, and very substantial on-chip buffers.

All that processing power and memory raises the question of interconnect. Particularly with programmable engines, a packet’s path through the chip can vary quite a lot. So fixed interconnect-especially pipelines-can be quite problematic, forcing circuitous paths on the packets. Busses, in contrast, are marvelously symmetric but can begin to saturate if packets have to visit several engines, introducing a quite unwelcome non-determinism. LSI’s solution is a proprietary non-blocking crossbar switch supervised by an out-of-band signaling system that manages congestion in the processing sites. Externally, the chip provides XAUI ports for 10 Gbit Ethernet, SGMII, SRIO, PCIe, and no less that three DDR3 ports.

In contrast, the APP3100 communications-processor SoC has a pair of relatively modest ARM-11 cores pretty much dedicated to control-plane tasks. In the data plane, the chip employs a multi-engine classification processor, a multi-engine traffic manager, and a security accelerator. The chip is intended to provide Carrier Ethernet or enterprise security services to 1 Gb/s packet streams without the use of external RAM.

The notion of ganging IP blocks to increase packet-processing rates can apply within a functional blocks as well as at the chip level. LSI’s third announcement, the Tarari T2500, is a 65nm content and security processor that is itself a multicore SoC. The chip contains five regular-expression evaluation engines, each of which can run up to 12 concurrent threads. Threading is possible, according to LSI Tarari marketing manager John Bromhead, because of a unique design that allows an engine to start a dozen evaluations on different parts of a packet and run them at the same time. The resulting throughput-up to 20 Gb/s for security screening and up to 160 Gb/s for application recognition, is equivalent to having 60 regular-expression processors in the chip.

The notion of building a base of processing elements and then a technology for quickly combining them in different patterns to address different customers’ intended data flows has a lot of appeal to it. But integration issues, including interconnect architecture, clocking architecture, power-management strategy, and debug provisions, make the integration phase of such an SoC design a major undertaking in its own right.