Clocking and Intel's Queensbay platform: SoCs in embedded design

We have remarked before that SoC designers can inadvertently create some very serious challenges for board designers. Often this happens when the integration level of the SoC forces board designers to deal, on a few square cm of one board, with signals that had been spread across several boards in previous designs. But another frequent issue is clocking. Clock requirements that look entirely reasonable to an IC physical-design team doing a 90nm SoC may look completely daunting to board designers who have to generate and deliver all those clocks to tight specifications, often with the assistance of somewhat questionable low-priced PC board suppliers.

Chip designers in different markets have taken different approaches to the clock issue. Some microcontroller designers have gone to great lengths to protect their embedded-design customers from the internal clocking complexities of the chips, even as the speeds and numbers of internal processors have increased. The microprocessor business, and especially the PC CPU business, has been at the other extreme, demanding ever more clocks at higher frequencies and to tighter specifications. These demands have created an entire sub-market that supplies clock-generation chips for specific Intel motherboard reference designs.

So what happens when Intel-which launched its most recent microcontroller before some of today’s engineers were born-designs an integrated platform for embedded computing? The recently-announced Queensbay platform offers an answer. The platform includes two major chips: the Tunnel Creek Atom-based SoC, with its on-chip graphics DDR2, and PCI Express gen2 controllers, and a choice of several I/O hubs such as the Topcliff. The two chips are linked by the PCIe bus. Running the Atom CPU at between 600 MHz and 1.3 GHz, the chip set is aimed at embedded applications such as digital signage that are graphics-heavy and compute-intensive.

Queensbay presents an interesting challenge for board designers-not so much because of the frequency of the clocks as their sheer number and tight specifications. There are 100 MHz clocks for the CPU, PLL reference, and PCIe blocks, a 96 MHz pixel clock, and various slower clocks for other I/O controllers in the hub chip. The fastest clocks are generally differential-mode rather than single-ended. If designers choose to develop their own I/O hub chip, they can complicate the situation even further.

SpectraLinear, which has been focusing on integrated clock ICs for embedded computing, is out almost concurrently with Intel’s Tunnel Creek announcement with a family of clock chips for Queensbay. A look into their design might be instructive.

There are four standard-product chips in the family, providing a variety of combinations of the number of clock outputs at various frequencies and the choice of 48- or 56-pins, and QFN or TSSOP packages. Each chip provides all the clocks necessary for a particular Queensbay configuration. The company is also using the design as the basis for developing custom configurations.

A couple of the features in the SpectraLinear SL28EB7xx family suggest some of the issues board designers must face in working with the Queensbay platform. One such feature is Wake-on-LAN support. Topcliff has a 1 Gbit Ethernet port, and the chip set offers a mode in which everything sleeps except a low-frequency LAN monitor circuit. When a packet arrives, Topcliff wakes up the rest of the chip set. In order for this to work and save power, the clock generator provides the low-frequency clock for the monitor circuit, and shuts down its other clock generators while the set is asleep, waking up its clocks in time to serve the awakening Queensbay.

SpectraLinear is also offering its EProClock option on these chips. EProClock allows designers to select a wide range of detailed timing and electrical characteristics for each output pin, including frequency vernier, phase, rise and fall times, and output impedance. These options can be preprogrammed at the factor so the clock boots in the configured state. SpectraLinear vice president of marketing Elie Ayache said this capability has factory turn-around of as little as a couple of days, so designers can tune the clock chip to the circuit board their vendor is actually delivering, instead of attempting to design-and pay for-an ideal board.

Ayache offered another example as well. The various clocks in the Queensbay platform may be asynchronous to each other. If you tune them so that the frequencies and phases don’t quite match, you avoid having major coincident-switching spurs in the emission spectrum generated by all the possible PCIe channels transitioning at once. Spreading out the transitions can be a big help in achieving emissions certification.

A quick look at one vendor’s approach to clocking the Queensbay platform may not provide a template for all possible situations, But it does offer embedded designers who are used to lower frequencies and less demanding interconnect a glimpse of what they are up against. In that respect it is worth studying.