Sun and Xilinx team to make OpenSPARC a physical reality for researchers

Since the announcement of the OpenSPARC T1 CPU core, students, researchers, and interested parties elsewhere have had free access to the RTL for a multithreaded Niagra UltraSPARC CPU design. And there have been literally thousands of downloads under the GPLv2 license, according to Sun’s senior director of front-end technologies and the OpenSPARC Program, Shrenik Mehta. But for most of the downloaders, experimenting with the RTL has been a theoretical exercise—there was no affordable and straightforward way to realize the RTL in hardware.

Today, Sun and Xilinx announced an extension of an existing agreement that will at last give a physical reality to the OpenSPARC program. The two companies have developed an OpenSPARC T1 Evaluation Kit. The kit is based on a board carrying a Xilinx Virtex-5 LX FPGA and supporting hardware. Accompanying the board in the package will be Xilinx SystemACE software sufficient to allow the user to boot Solaris on the board, and of course the OpenSPARC T1 RTL. Users will have to have their own Xilinx tools license. The package is available immediately through Digilent for $1999, with special discounts for academic customers. Sun is also running a university grant program to make the kits more widely available in the academic world.

The RTL allows for configuration of the core to suite the user’s requirements, for instance by adjusting the size of the TLBs, or by selecting how many concurrent threads the hardware should support, up to four threads per core. In addition, the Evaluation Board uses the RocketI/O transceivers on the Virtex 5, configured as Xilinx’s proprietary Aurora high-speed link over serial ATA cables, to support Sun’s inter-core packet protocol. So up to four boards can be connected together into a multi-core configuration.

Given that the T1 is a Niagra-class 64-bit CPU with hardware multithreading, the fit into the Virtex-5 is surprisingly effective, according to Xilinx senior design engineer Paul Hartke. A single-threaded T1 core requires about 40K LUTs, Mehta said, and Hartke added that it will run at 62.4 MHz. While this is not groundbreaking speed for a microprocessor, it is sufficient to learn a great deal more about multithreaded, multicore architectures than can be learned from RTL simulation. Mehta emphasized that this is a real, 64-bit, server-class CPU, not an embedded-computing CPU that has been shrunk for FPGA implementation. It is architecturally suitable for studying enterprise-level topics such as virtualization and dynamic task scheduling in multithread environments.

And there is another area of research that Mehta and Hartke hope to stimulate with the kit: optimization of processor-core RTL for implementation in FPGAs. "Initially, we just took the OpenSPARC RTL and ran it through the Xilinx tools," Mehta related. "We ended up with a design that took about 150K LUTs. At that point, we started to get an education from the Xilinx people about adapting designs to FPGAs."

"Even at that, this does not represent an optimized design," Hartke emphasized. "We essentially just cleaned the RTL up a bit and ran it through the synthesis tools to get to 40K LUTs and 62.5 MHz. There is a lot more that can be done, and I hope this question interests some researchers."