Altera takes the next step: FPGAs in 40 nm CMOS

Altera’s announcement this morning of the Stratix IV and Hardcopy IV FPGA and structured ASIC families offers some fascinating insights into the direction of the programmable logic market, the direction of the overall SoC business at advanced geometries, and in particular at the challenges of migrating to 40 nm. We will have much more detail on the latter topic in an upcoming EDN Magazine feature, so let’s focus on the former: where FPGAs and SoCs are headed.

The top-level facts are in the numbers. The largest chip in the Stratix IV family has twice the raw gate capacity of the largest Stratix III device. Other capacities have grown similarly, with the largest devices having up to 23 Mbits of embedded RAM (not counting logic cells used as memory), almost 1400 multiplier blocks, or up to 48 high-speed I/O transceivers.

The next level of detail is also in the numbers, but not so obvious. Altera focused this chip development from the outset on density and power, not on speed. Performance compared to Stratix III is relatively flat, according to the company, with the ability to clock meaningful blocks of logic in the chips’ core area at around 350 MHz. Remarkably, power consumption is also relatively flat. Altera senior director of product marketing David Greenfield says that leakage power is about the same, in mA/square cm, as in the 65 nm Stratix III. And the core voltage has been lowered to 0.9 V, giving the chips a break in both static and dynamic power.

This is no small achievement, given the characteristics of 40 nm transistors and the horror stories we have all been hearing about the growth in sub-threshold and gate leakage with decreasing geometry. To some degree, the savings are due to very careful design. Altera engineers exploited the triple-oxide capability of the TSMC process to reduce leakage wherever timing margins allowed. But Stratix IV also relies heavily on the multi-threshold technology Altera introduced in 65 nm. In this approach, each group of eight logic elements shares a common well with programmable back bias. So the timing tools can determine slack on each net and then select the back-bias tap on each set of logic elements in that net to provide either fast switching or low leakage.

Another area not so obvious from the top-level numbers is the amount of design work that has gone into the transceiver complement on these big dice. Altera is specing the transceivers in the GX variant of the new family at up to 8.5 Gbits/second, and offering PCI Express (through hard macros) for both generations 1 and 2. The transceivers are beefy enough to support the KR backplane serial interface spec at 8.5 Gbit/second. The company is not yet verifying 10 Gbit compliance.

Needless to say, given that this is a new family in a new process, there is a lot of design work, and some really good war stories, behind these transceivers. There is also a huge investment in signal-integrity verification—a particular challenge for FPGAs since it is virtually impossible to specify a priori what the electrical environment around a critical high-speed net or pin will be. Users are full of surprises. Suffice for now to say that elaborate test chips for the transceivers and clock-data-recovery circuits, and close joint development with TSMC, were vital to the design.

At an even less visible level, Stratix IV should be a reassurance to a lot of SoC design teams looking warily at the move beyond 65 nm. According to Greenfield, there were no significant changes to the architecture of the FPGA, the structure of the logic blocks, or the routing approach between 65 and 40 nm. In fact one of the early test chips through the TSMC foundry was reportedly a full FPGA, ported directly from 65 nm to 40 nm, which the Altera and TSMC engineers used as a vehicle for exploring the design space in the new technology. Many things changed from that first set of masks, but the underlying FPGA architecture was apparently not one of them.

That underlying architecture recurs in the HardCopy IV line, which is worth exploring in itself, and in a subsequent post. That, in turn, presented a layout problem, because now Altera had to fit transceivers and CDRs that did not shrink into the periphery of a die that had shrunk considerably. As a consequence, you can only get a maximum of 24 transceivers on the Hardcopy family, as opposed to the maximum of 48 on the equivalent Stratix devices. Power dissipation of the interfaces will also stand out more on the Hardcopy parts than on the FPGAs, at about 125 mW per channel at 10 Gbits/s.