Magma Tekton: rethinking static timing analysis

The biggest innovation in STA in recent years has been SSTA. However I would argue that most of the innovation in SSTA is actually in the efficient characterization of the library models and the creation of statistical SPICE models that feeds SSTA characterization. Designers have been slow to adopt SSTA I think for two main reasons: 1) It's new, so there is only limited proof that it really works in silicon; 2) The IP vendors are not supplying the libraries as this is an additional burden for them. I believe 1) will be solved in due time; for 2) customers will search for tools and services from vendors who can provide SSTA libraries for ALL commercial SSTA tools. We are certainly one of just several vendors and, in my mind, the most comprehensive vendor to provide SSTA tools and services.

Performance in STA had improved on single core. When you are comparing performance, you have to bear in mind that delay computation models have changes a lot requiring more computation and chip sizes have increased exponentially in those 15 years. Yes the compute power also improved but my and large STA have kept pace on performance. Your statement that every net can be computed in parallel is not completely true. Most rely on computation of fanin and adjacent nets.

EdaGuy: Thanks for making a whole bunch of excellent points. I should have been more clear. All of the items you listed of course were significant changes in STA tools. But they addressed accuracy or new analysis needs, not performance. I think that was what Magma was saying. I would love to discuss further whether statistical timing is an evolution of STA, though. I see your point that it is a step to solve the same basic problem in a more complex environment. But I wonder if the low adoption rate outside of IBM is because SSTA is so unlike STA in the way people have to think about its results. In any case, as always thanks for reading closely and adding information to the post. ron

That being said, if your point was "has the leader in STA aggressive kept up with user's needs or even gone far enough to more than exceed what they need and actually do their wishes too"... I would agree the answer is no. Unfortunately in the world of EDA, typically it takes a new entry in the market to cause someone to innovate their bread and butter. Most companies realize this after its too late. Dracula RIP.

I will not grant you not much has changed in STA in 15 years. Let's see, off the top of my head: 15 years ago we used a very simple timing model, either a constant cell delay, or a delay as a function of output load. Then came CMOS4 models. Then came resistance and AWE, and now more complex algorithms for wire delay analysis. Then came SI impact on delay. Then came OCV. Then came CCS models for both delay and noise. Then came AOCV. Then came voltage scaling and multiple voltage domain analysis. And SSTA is not a separate subject, it is merely an evolutionary step in the design margining which started with the baby step of OCV. Ya, alot of people aren't using it yet, and its computationally very complex. But its not a separate subject. OK, so that's from the delay calc standpoint. 15 years ago, chips were small. Many were single clock systems, or maybe a few clocks. Today's larger chips have 50-100 clocks or more. That causes your number of timing exceptions to increase dramatically. Or maybe you can show me your "set_false/multicycle_path" file from your 15 year old chip. Oh ya, and generated clocks. And clock trees. (ya, remember, 15 years ago most clock trees were a "trunk" drawn with a fat wire and large clock buffer) And the multicore stuff... that's something the "big guys" haven't done until recently (and only when Extreme and CLKDA came up with it) Now maybe it took them 15 years to get multicore right. Or maybe they aren't incentivized to make their tool faster because that would mean I could buy less licenses... their only incentive is to make their tool just fast enough that I don't switch to their competition. So remind me again, how has "nothing much has changed since"? Please, when you talk to EDA vendors, don't just repeat their marketing catch phrases.

Designers need up front modeling in their design flows to prevent timing problems downstream. But what front end modeling tools are out there for designers to use?