Altera and 40 nm, again: Hardcopy IV coincident with Stratix IV

One interesting facet of Altera’s Stratix IV announcement this morning is that the company is announcing the Harcopy IV structured ASIC at the same time as the FPGA. In fact, it appears to have released Hardcopy IV and Hardcopy III together—the former at 0.9V core voltage, and the latter at the higher core voltage used in Stratix III—but both using the same 40 nm TSMC process. This appears to reflect the growing importance of a migration path from FPGA to cost-reduced, power-reduced device in Altera’s strategy.

The concept behind Hardcopy is simple. Users should be able to develop and verify a design on a Stratix IV device, submit the netlist to Altera, and get back a mask-configured version of the design, still in the same architecture but with substantially smaller hard connections replacing the SRAM-switched interconnect of the FPGA. Beneath that simple idea, though, there are some interesting complexities.

One such detail is the actual porting process. At the architectural level the Stratix and Hardcopy devices are nominally compatible. Altera has replaced the LUT-based logic elements of the Stratix family with what it calls H-cells: 18-transistor cells that are mask-configured for logic function, but that still have the ability to emulate the Stratix logic cell’s ability to use its LUT as SRAM.

The configuring of the logic cells and of the interconnect Altera does with four layers on only two masks, presumably exploiting TSMC’s multi-layer mask option. Unfortunately for the mask shop, these layers are all at minimum pitch, and so require full OPC treatment. The potential for lithography-rules problems is mitigated, according to Altera senior product group director Paul Hollingworth, by use of restrictive design rules on these layers. Still the NRE for Hardcopy IV goes up to around $400K, a third greater than for Hardcopy II. On a per-gate basis, this will probably work out to a reduction in NRE on the largest designs, given the increased capacity of the Stratix IV line.

Even though mapping a design across from Stratix to Hardcopy is pretty mechanical, there is still verification work to do on the Hardcopy design. Ironically, this is because the mask-configured interconnect on the Hardcopy chips is so much faster than the switched interconnect on the FPGAs. "A good part of our design centers’ work is checking for hold-time violations on the Hardcopy design," explains Hollingworth. "The Hardcopy design requires its own set of PrimeTime SI checks as well."

The high-speed I/Os in the Stratix GX family present another interesting issue. In theory, it should be possible to simply make the programmable features of the transceivers and CDRs mask programmable, shrinking and probably speeding the interfaces. But in fact, some Stratix users rely on being able to reconfigure the I/Os—especially the transceivers—in-circuit, to adapt to changing board configurations or electrical environments. So Altera chose to make the fast I/Os on the Hardcopy device SRAM-configurable, identical to the ones on the Stratix IV GX.

One more interesting wrinkle in the Hardcopy story is that some users, according to Altera’s Hollingworth, are starting to think of the Hardcopy chips as something more than just an inexpensive replacement for the Stratix FPGAs. "We are seeing some customers now who are interested in running their designs much faster in the Hardcopy parts than they ran in the FPGA," Hollingworth observes. This could be an interesting situation for the Altera design centers, which are set up to preserve timing in the transition, not to accelerate it. But it could also provide a whole new dimension of interest in the Hardcopy concept. The whole idea appears to be blossoming at 40 nm to a degree that structured ASICs were never able to achieve at 130 or 90 nm.