Apache Totem offers full-chip power- and noise-integrity analysis for chips with analog content

The problem of power and noise analysis in SoCs doesn’t need much introduction. Such analyses have been a standard part of digital SoC flows for a couple of nodes now, and most design teams would no sooner dispense with them than they would skip timing sign-off. But the same can’t be said so glibly about SoCs with precision analog or mixed-signal content. The digital power-integrity and noise-analysis tools are not particularly informative for analog designers, who have been pretty much compelled to rely on their proven analog simulation tool kits to extract information about power-integrity and noise.

But conventional analog simulation tools have their own problem: because they are general-purpose simulators rather than purpose-built analysis tools, SPICE and its offspring lack the speed and capacity to cope with a full-chip design after you put in all the power nets, clock nets, and parasitic paths. Andrew Yang, CEO of Apache Design Solutions, "Conventional analog simulation is not going to be able to handle above about 1 million transistors with parasitics included." That means designers have to cut the design into bite-sized pieces in order to complete the analysis.

But that cutting process can be perilous unless you already understand the fundamental noise and power-rail-integrity relationships on your die. Yang pointed out that structures that might appear quite isolated from each other could in fact be closely coupled at a sinister level. A modern compiled memory block with power-gating, for instance, should be pretty much correct by construction. You expect the compiler to take care of power transients and noise issues when it generates the block. And yet, Yang said, the block may have a major impact on its neighbors: there can be a substantial inrush current when the power-gating circuitry powers-up the block, causing IR drops throughout the local neighborhood. And there can be significant substrate coupling of fast transients from the memory into surrounding analog circuits. Any analysis that minimized these coupling path implicitly by the way the design was partitioned to fit the tool would come up with wrong answers.

Apache’s solution to the problem was to create a power and noise analysis tool—Totem—that works in the analog domain, but is fast enough for, as Yang claims, 100 million transistors with parasitics in an over-night run. To do this, the company made a number of major departures from the traditional SPICE approach to analysis.

First and most obvious, Totem analyzes the GDS-II files, not the netlist. "Netlist-driven analysis was really intended for functional verification and digital timing closure, not for analog power and noise analysis," Yang observed. "Working from the netlist for this kind of analysis would make the set-up process very error-prone."

In order to know what it’s looking at, Totem also uses the detailed standard parasitic format (DSPF) file, Yang explained. But the operations of the tool and its interaction with the user are organized around the polygons.

Apache has resorted to a number of clever schemes to improve the performance of the tool. Many of these are becoming popular in full-chip analysis circles, and some are rather unique. For example, like many other recent tools, Totem uses mesh pattern recognition to identify portions of the design in which it can reuse a single model to represent a number of identical patterns.

Much more significantly, and probably uniquely to Apache, the tool requests a stimulus file from the user, and then analyzes the stimulus file to determine the exact operating points of the transistors in the design. This information allows the tool to selectively pare down the BSIM transistor models until they are just accurate enough over the range in which the devices will actually operate. Totem then employs the user’s simulation tool to analyze the models. In this way the model analysis portion of the job will be consistent with the user’s other simulation runs.

Totem then has a number of internal analysis engines that set about cranking the transistor models, DSPF file, and GDS-II file to analyze the power and noise characteristics of the chip. One of the advantages of working at the GDS-II level, Yang says, is that if the user doesn’t like what she sees, she can simply do a quick polygon edit and rerun the analysis, without having to iterate through a placement, routing, and extraction.

Yang said that various versions of Totem have been in the hands of early users for about two years. Now, after considerable feedback, refinement, and a major test chip done jointly with STARC and Kobe University—which combined a 400 MHz processor with several analog subsystems—the company feels ready to do a public release of the product. So here it is.