Doing integrated RF at 45 nm: an ST perspective

There has been a great deal of debate—but very little data–about the viability of integrated RF circuitry in 45 nm SoCs. One line of thought has always maintained that it was no big deal, since transistors are even faster at 45 nm than at 65 nm. Another line of thought argued that increased process variations, increased noise, poor linearity, and reduced dynamic range would render serious RF design all but impossible, and would certainly demand major revision of circuit designs. Now we have some actual experience to add to the opinions.

ST Microelectronics announced recently that they have produced working RF circuits in a variant of their 45 nm process. The announcement not only suggests viability of 45 nm for RF chips, but hints at the viability of integrated RF for 45 nm SoCs, depending on just what is hidden under that little word “variant.”

Richard Fournel, technology line manager at ST, offered some more detailed information on the company’s achievement. He said that the design team in fact made “only small modifications” to the standard 45 nm digital process for the RF design. The real basis of the work, he claims, is a set of very accurate models for the RF devices, including in particular accurate modeling of linearity, gain, and noise. Without accurate device models, porting to 45 nm would indeed have been a serious risk.

Much of the team’s work, he said, went into noise, and much of that was specifically on 1/f noise. Early modeling led to exploration of the impact of such issues as oxide formula, implant doses, and gate structure on this poorly-understood noise source. ST’s 45 nm process, by the way, uses a silicide gate structure without high-k. “We are still suspicious of the noise characteristics of high-k dielectrics in this frequency range,” Fournel said.

The other major effort in the device-design area was to redesign the passive devices for the new process, reducing both the vertical and horizontal dimensions so that the passives would scale at least a little bit between 65 and 45.

ST ported a complete zero-IF chain, including LNA, mixer, and a 7.4-bit A/D converter to the new process. Fournel said that from a circuit designer’s point of view, once the basic device structure was worked out there were not really that many changes between the company’s current 65 nm process and the new 45 nm process. The new process does in fact provide excellent f_t, allowing very good gain—over 200 for standard devices–at radio frequencies. And the process is quite stable as long as you avoid minimum geometries, Fournel reported.

As a result of their experience, ST does not see the end of the world for integrated RF at 65 nm. In fact, Fournel suggested, the performance of 45 nm as an RF process was sufficiently good that it could encourage more designers to switch from BiCMOS to RF CMOS in the future. And so yet another doomsday scenario for process scaling may be turning out to have been premature.