Cadence Encounter Digital Implementation System 9.1: avoiding incorrect by construction

One of the most serious problems with design flows for 32 and 28nm designs, aside from the sheer complexity involved, is what you might think of as an impedance a mismatch between the flow and the process. Design flows are capable of creating a far wider range of logically-correct, timing-closed designs than will pass the increasingly stringent rule checks, design-for-manufacturing recommendations, and extractions that have to happen for sign-off. This is basically the same problem we had years ago with timing closure, but now with a much wider range of variables: the information available to the designer and to the tools early in the flow is not a good predictor of the design that comes out the other end. And so there are iterations. Lots of iterations.

Cadence, with release 9.1 of the Encounter Digital Implementation System, is trying to help. It seems logical that the only way to avoid iterations from sign-off all the way back into the physical design flow—or worse—is to have sign-off-quality data on RC parameters, timing and power, litho compliance, and so on from the beginning. But except in the case of physical IP blocks, this is clearly impossible. You can’t look at a pile of Verilog and tell whether the resulting geometry is going to be litho-compliant. On the other hand, you might be able to tell if it is unlikely to be.

The obvious objections are manifold. Early in the design the structures are too abstract to make even guesses about the characteristics of the physical design. Even if it were possible to make such estimates, we learned from our experience with timing estimation that estimators that use different algorithms from sign-off tools will fail to predict the sign-off results, and lead the design off in the wrong direction. And even if there were tools that could produce good estimates, the computing time and database sizes involved would be impractical early in the design, when so much is changing so rapidly.

Cadence appears to have taken on all these issues. The underlying technology, according to product marketing manager Rahul Deokar, rests on a number of innovations. The first is a new data abstraction, which Deokar says reduces the volume of design data by two orders of magnitude compared to netlist form. The new abstraction captures not only the design structure but timing and power estimates, even for blocks with incomplete netlists.

The second innovation is a way to modify Digital Encounter’s sign-off analysis tools—specifically for RC extraction and litho hotspots—to run much faster with the abstracted database then they would on a full sign-off database. This allows the analysis tools to run essentially concurrently with the design tools, identifying structures that could give trouble at sign-off when they are being created, rather than nine months later. The analysis system supports all current 32nm and 28nm rules, Deokar says, so that designs are likely to arrive at DRC actually compliant with the design rules instead of decorated with violations.

Finally, this ability to estimate the impact of design decisions early in the flow just begs for architects to explore more of the design space. If you are warned when you are about to step in wet paint, you are more likely to look in all the rooms. So Cadence has included an automated floorplan synthesis capability that, coupled with the estimation tools, lets chip architects try out a microarchitecture, generate a floorplan, and see the implications for key design parameters right there. There is also an incremental-design capability for dealing with ECOs.

Deokar says that the system has been in the hands of a few customers, such as Hitachi, NEC, and Teranetics, for some time now, and everyone is reporting significantly reduced iterations through the digital flow. But these results appear to have been at 45nm and above. So it remains to be seen just what users’ experience will be in the far more demanding world below 40nm, and, for that matter, how well reduced design iterations reflects improved silicon quality.