Solido design attacks variations in transistor-level analog design

There is a gap between the variation data that foundries provide to their customers and the ability of analog designers to actually use the data, according to Solido Design Automation president and CEO Amit Gupta. Instead of using the statistical variation data that’s actually there in the design files, Gupta says, many analog designers rely on digital process corners in attempting to understand the variation sensitivity of their designs. Since the digital corners may be nowhere near the corners that are important to the behavior of an analog circuit, this can result in either substantial overdesign or serious yield problems.

Solido recently introduced Variation Designer in an attempt to deal with this problem. As described by the company, Variation Designer is something of a platform into which Solido can plug specific application packages. The platform takes in schematic-level netlists, SPICE model libraries, and nominal device-size data; and provides interfaces to the tools in the design team’s existing simulation cluster, plus an environment for executing Solido plug-in applications.

The first of the plug-ins to be announced is the Statistical Applications package. This set of tools accepts whatever global and local statistical variation data the foundry provides, identifies its own set of process corners, and performs a set of services for the designer, all using the team’s current simulation tools.

Rather than attempting a full statistical analysis approach to analog design, the Solido tools approach the problem by identifying their own set of process corners, which the company calls True Corners. Based on Variation Designer’s analysis of the foundry data, these corners attempt to capture not fast and slow digital corners, but corners for the finished analog circuit’s figures of merit. For example, the True Corners for a circuit might include the best and worst cases for dynamic range and phase margin. This could presumably lead to a lot more corners than the four typically used for conventional digital design, but the new corners might actually be useful.

The alternative, according to Gupta, is for the design team to ignore the digital process corners and sweep the entire process space—again using the foundry variation statistics—with a Monte Carlo analysis. This is entirely possible, Gupta emphasized, and could identify new corners for the design. But it would be so time-consuming that virtually no one actually does it.

Variation Designer gives the design team another option. Working with the True Corners, the Statistical Applications package performs a scan for vulnerable points in the design, and then does a full sensitivity analysis. It also does a mismatch analysis using the corners. All of these analyses give the design team clues for making changes to the topology or sizing of the circuit, with some numerical guidance on just how much margin the design needs for a given level of yield.

Finally, once the design team is happy with the design, the package performs a more exhaustive verification, using either full Monte Carlo or Latin Hypercube sampling, and estimates yield. The process, according to the company, is one to three orders of magnitude faster than a Monte-Carlo-based approach.

All of this requires not only well-coded algorithms, but tight relationships with foundries—to get the data—and EDA vendors—to get the tool interfaces. Solido claims to be working with TSMC, UMC, and the Common Platform Alliance on the foundry side, and with Cadence, Mentor, and Synopsys on the analog design-tool side.

The Statistical Applications package is intended just to deal with random process variations, such as occur at all geometries starting at about 90 nm. But Gupta said that as you approach 32 nm, two other sources of variation will become more important: well-proximity effects and stress effects. Both of these impacts on transistor performance are highly pattern-dependent and less random in nature, so they are poorly-modeled using statistical techniques. Consequently, Solido is planning to offer an application package for each of these in the future.

Corner-based approaches have been highly controversial in the digital domain, with some foundries—notably IBM—requiring full statistical timing analysis, while some fabless semi houses claim that they can get just as good a result with a moderately large number of traditional corners. But there doesn’t yet seem to be any such debate between corner-based and statistical analyses in the analog world, at least in public. Whether application-parameter-based corners will be sufficient, or whether they will be a stepping-stone to a full statistical analysis of analog circuits—maybe using supercomputing clusters—remains to be seen. Solido clearly has come down on one side of the question.