A look into the future of FPGAs with Xilinx's Gavrielov and Rangasayee

The argument between ASICs, ASSPs, and FPGAs has ranged over the same territory for a decade. FPGAs are slower, more power-hungry, and more expensive than comparable ASICs. But FPGAs require no NRE, require little physical design or verification, and provide prototypes in hours or days instead of weeks. In outline, the terms of the debate haven’t changed: FPGAs make sense for low- to moderate-volume designs of low to moderate complexity, in which neither power nor performance is critical and there is no close fit in the ASSP world.

But this apparent stasis conceals a lot of activity at the margin, where the technologies have significant overlap. In part this activity is a gobbling of market share by FPGAs as a result of the global economic catastrophe. With end-user demand all but gone and returning only furtively, "moderate volume" includes a lot more designs than it used to, especially if management uses the 90-percent-confidence forecast instead of the "this is what it could do after a recovery" forecast. And that part about no NRE looms very large when there is no cash available for NRE.

Technology has shifted the boundary as well. A moderate-density, moderate-performance design for a 40nm FPGA might be a challenging design for a 90nm ASIC or an aging ASSP—you always have to be careful in this game to compare apples to apples. As technology advances, more and more legacy sockets become feasible for FPGAs.

Yet the big inroads into enemy territory have in the past come when FPGAs have integrated hard IP blocks for specific applications. When designers put hard DSP blocks into FPGAs, the chips became one of the best ways to accelerate the inner loops of signal-processing algorithms. When they added numbers of high-quality SerDes blocks, FPGAs became the cheapest way to originate or bridge to a multilane high-speed serial bus.

So what now? If transistor performance takes another jump with high-k/metal-gate processes at 32nm, FPGAs will continue to lag leading-edge ASICs and ASSPs in performance. And they have no full answer—Altera’s selectable threshold voltage notwithstanding—for the many advances in dynamic power management in the SoC world in recent years. So FPGAs still aren’t going to grab the headline sockets. But FPGA designers still have surprises to offer. In conversation last week Xilinx president and CEO Moshe Gavrielov and vice president of corporate strategic planning Krishna Rangasayee discussed some of their thinking on the future of the devices.

Part of that future involves the customer’s design process. "Customers have been pushing system design capability back onto silicon vendors," Rangasayee said, "keeping just the expertise they need to differentiate their products." This has led to silicon vendors having to provide full manufacturing-ready system reference designs to even get in the door at many OEMs.

"But the model of silicon vendor as system integrator is broken," Gavrielov added. "It’s a trap: the silicon vendor can’t make any money." The Xilinx executives say that as FPGAs gain access to more demanding SoC sockets—which they certainly will—the FPGA design flow must recognize how the design skills of systems OEMs have changed. But Xilinx must not try to become a systems integrator.

In practice, this means providing customers with a design interface that exposes the details relevant to differentiating their design, abstracts away the details the customer doesn’t need, and provides the IP the customer requires. "We should give the OEMs the 40 percent solution so they can do their 60 percent," Rangasayee said. At the end of an evolutionary trajectory that has already begun, this means application-specific design flows for configuring the FPGA chips.

And part of the future involves increasing specificity in the FPGAs themselves, although vendors are loathe to put it that way. "You will see a larger portion of hardware solutions, without compromising the flexibility or the fundamental horizontal nature of FPGAs," Gavrielov said.

Rangasayee elaborated with a case in point. "There are other IP blocks that naturally are associated with high-speed SerDes blocks across a range of applications. For example, many kinds of packet-processing engines require encryption, traffic management, layer-seven inspection, intrusion detection, and interfaces to switch fabric." As wire speeds increase, these blocks are migrating from software or even from programmable fabric to hardware. "You could see such IP getting hardened while still leaving room for a lot of customer differentiation in an essentially horizontal part," Rangasayee said.

Interconnect is another area that may come in for change. Traditional FPGA fabric emphasizes regular structure and predictable timing so it can connect logic cells to implement IP blocks. But today, users have to rely on that same interconnect structure to connect the IP blocks themselves together. This can mean, for example, implementing an AMBA AXI fabric in the interconnect segments and switches of an FPGA: not an optimal implementation of a critical resource.

The relationship described in Xilinx’s recent joint announcement with ARM will address this issue, Rangasayee suggested. And in the longer term, Xilinx researchers are exploring how one might implement a network-on-chip structure in an FPGA, without knowing a priori the shapes or locations of the IP blocks to go into the fabric.

Another fundamental issue is memory. The available block RAM on today’s large FPGAs is dwarfed by the on-chip memory in today’s most challenging SoCs, and even for the latter memory is a scarce resource. Gavrielov suggested that the solution to this problem is not to make FPGA dice even larger with massive amounts of block RAM, but to move into the third dimension. "Customers will at some point in the future look to heterogeneous silicon assemblies to solve these problems," he said. "In the future, more than one die in a package will be mainstream." Gavrielov said that Xilinx is watching closely the evolution of through-silicon via technology. "Today the problems appear to be more organizational than technical," he said. "Getting known good dice and agreeing on who owns the responsibility for the stack can be more complex than creating the vias and connecting them."

While they freely discuss adding diffused functions—some of them quite dedicated—to the hardware of FPGAs, Gavrielov and Rangasayee clearly remain committed to the model of the FPGA as a horizontal, mainly-configurable device. Given that the FPGA market has already taken in stride domain-specific features such as DSP blocks and SerDes blocks, the new additions to some members of mid-sized FPGA devices should be no obstacle. And the superior energy-efficiency and performance of diffused functional blocks will move FPGAs another increment closer to parity with the always-elusive leading-edge ASICs and ASSPs, even as those devices continue to increase in development cost.