Altera announces Stratix V

Following their technology announcement by about three months, Altera this morning announced their first 28nm FPGA product: Stratix V. The family will consume just about the first wafers out the door from TSMC’s 28HP process, with sampling scheduled for the first quarter of 2011.

Both Altera and TSMC have tried to manage expectations about 28nm, and the Stratix V follows that pattern. "The focus for our high-end products is on bandwidth for networking applications, not on raw logic speed or gate density," said Altera senior director of component products Luanne Schirrmeister. And indeed, the introduction spends a lot more time talking about transceivers than about the logic fabric. But there have been substantive changes to both.

The big story on the transceivers, of course, is 28 Gbit/s speed. The announcement contains both the 28 Gbit headlines and some of the fine print that, as they say, taketh away. For example, 28 Gbits/s is the maximum chip-to-chip rate on a very well-controlled PCB trace, for a limited number of transceivers. The speed limit for more demanding backplane interconnect is 12.5 Gbits/s: still formidable. Another key point is that not all the transceivers on a given Stratix V will be 28 Gbit-capable. There are four separate product lines in the family. First out the door is GT, with up to 66 transceivers, only some of which will be 28 Gbit-capable. Then there are two other families, GX and GS, that will have transceivers in various numbers, but only the slower 0.6-12.5 Gbit designs. Finally, there is the Stratix V E, aimed at logic prototyping and such, which will have no transceivers at all.

The other big news in the technology announcement was embedded HardCopy blocks. As promised, Altera is initially using these to support high-speed interface logic to back up its transceivers. Schirrmeister said that the first chips to use the capability would have the equivalent of 700K logic elements of embedded HardCopy—about 14 M gates by Altera’s somewhat marketing-driven reckoning. This capacity will go into functions such as DDR3 controllers; 10G Ethernet MACs; CPRI, Interlaken, and SRIO controllers; and PCIe Gen 3 controllers. By combining the blocks in various ways, Altera will produce application-directed FPGAs for various specific sockets, including linecards for the 40G/100G Carrier Ethernet buildout, base-station upgrades for LTE, and multiservice linecards for switches in access networks and data centers.

Less publicized in the technology disclosure were changes in the logic portion of the chip. These alterations will be partially or fully concealed behind the design-tool interface, but will positively impact implementation results.

One such change is a new design for the embedded DSP blocks. The blocks are now composed of 9-by-9-bit segments, and can be combined to form up to a 27-by-27 DSP. Cascading logic allows these 27-by-27 blocks to work together to form a 54-by-54 double-precision fixed- or floating-point unit. The partitioning and cascading logic is internal to the DSP blocks, so it does not require logic elements from the programmable fabric to stitch the pieces together. Further, the DSP blocks now contain two additional elements that previously demanded routing into the programmable fabric: coefficient registers and pre-adders. Altogether the new DSP blocks should be more efficient for mapping a variety of data path widths, should be faster because data will flow back into the programmable fabric less often, and should consume far less of the routing resources and logic elements around them.

There is a new 20 kbit memory block, implemented with true dual-port cells and operating at up to 600 MHz. This allows the largest parts to have up to 53 Mbits of embedded RAM, counting logic cells converted into SRAM along with the block RAM. And Altera has added a pair of registers to its logic module, so that the module now contains an 8-input look-up table, a pair of full adders, and four registers. Schirrmeister said that this bulked-up logic module was more efficient for implementing pipelines. And it is fracturable, so there is not so much waste when mapping less-organized logic into the more powerful modules.

With the first samples at about nine months away, target users in the high-end networking space will have plenty of time to get specifics about the HardCopy interface configurations and models from Altera, play with the design tools, and do trial layouts of the high-speed interfaces and their own functional blocks. This will be none too soon for line-card vendors who are already under pressure from carriers for 100 Gbit line cards. And the architects may be able to gather enough data to make an informed FPGA vs. SoC vs. ASSP decision. Altera is clearly hoping they can provide enough solid data on a future chip to tip the choice their way.