Announcement by D2S completes the picture for Fujitsu maskless eShuttle

Recent information from Fujitsu on their eShuttle IC prototyping and limited-production service has explained most of the technology involved in using the Advantest F3000 direct-write e-beam system to write patterns directly onto wafers at high throughput, making limited production of 65 nm ICs without masks practical. But the announcements have left an open question about how standard design data would get translated into files for the F3000 in the first place. That became clear this evening with D2S’s announcement of a relationship with Fujitsu to produce a PDK overlay and translation service to bridge from a standard industry IC design flow to maskless production.

D2S is a venture-backed start-up that specifically addresses the EDA needs of the eShuttle process. Headed by chairman and president Aki Fujimura, of Cadence fame, the company has developed a supplement to Fujitsu’s PDK and a translation program that together allow a design team to use a standard design flow to target the eShuttle service.

The foundation of D2S’s offering lies in the design of direct-write e-beam systems. Normally, the optical column of an e-beam system contains a pair of rectangular apertures, one above the other. By deflecting the beam as it passes between the apertures, the system uses one rectangle to partially mask the other, so that together the two apertures can shape the beam into any arbitrary rectangle or square. The e-beam system writes patterns onto the wafer by projecting a series of these rectangles and squares onto the surface, one after the other. Each image projected onto the wafer is called a shot. With enough shots, the e-beam system can create any pattern that is a right polygon.

But this is a very time-consuming way to project a mask layer onto a wafer. Anticipating this, e-beam system developers provide another alternative. The first rectangular aperture becomes a smaller opening, and the second aperture is replaced with a stencil mask that carries a large collection of patterns. These patterns could be shapes of gate electrodes, combinations of metal-1 patterns, or simply a basic set of complex polygons. By using these characters, as they are called, the system can expose a complex shape in one shot, if it already exists as a character, compared to the several or many shots it would take to build the shape up out of rectangles.

The big news from D2S’s point of view, according to Fujimura, is that at 65 nm for the first time entire interesting standard cells, including a RAM cell and a flipflop, fit within the area of one character on the e-beam system (about 4 by 4 microns on the wafer.) So it is possible to simply encode as character on the stencil for a given mask layer the pattern for each of the 45 most widely-used cells in Fujitsu’s cell library as characters, and insert that stencil mask into the F3000 system. Then most of the time, the e-beam system can print an entire cell in a single shot. Patterns not covered by the basic set of 45 cells (45 is apparently the maximum number of characters the stencil can hold) still get composed out of rectangles, one shot per rectangle.

This by itself can reduce the number of shots necessary to expose a layer by a factor of five, according to Fujimura. But the company goes one step further. By putting an additional cost function in the files the PDK provides for the synthesis tool, D2S is able to train pretty much any major ASIC synthesis engine to prefer the cells D2S has chosen to place on the e-beam stencil. By thus steering the design tools away from cells that have to be constructed piece-by-piece, D2S is able to decrease the number of shots by yet another factor of five.

The combination of cell selection and one-shot printing of most cells is enough to make the direct-write system’s throughput about 25 times greater than it was using the simple rectangle masks, allowing eShuttle to meet its production targets, according to the company. This should make 65 nm prototyping, early production, or full production of moderate-volume variants of an existing design economically quite feasible for most design teams. But not quite yet.

D2S has done numerous studies on paper to prove out this process, Fujimura says. Now the company is actually doing a test chip on Fujitsu’s 65 lp process. After they receive silicon, at some as yet unscheduled point in 2009, D2S will compare the chip they have produced against the chip Fujitsu has done using a standard design flow and mask creation process. Fujimura says he expects the D2S chip to have only about a 3 to 4 percent overhead in key parameters like power and area. But silicon will test this expectation. In the meantime, plans are underway for Fujitsu, eShuttle, and D2S to continue working together at least through the 40 nm node.