When a DSP chip makes sense: Analog Devices expands the SHARC family

It’s almost a reflex for FPGA users and SoC designers to integrate signal-processing hardware into their designs. After all, FPGAs can have embedded DSP hardware, and there is a plethora of signal-processing IP available, ranging from data paths to whole DSP cores. But sometimes it still makes sense to look at using a dedicated DSP chip.

It may be that the project is in such early stages that prototyping on a DSP chip is quicker, given the level of algorithmic changes coming through. Or that the expected shipping volume just doesn’t justify the engineering time to create a custom data path around the embedded MACs in an FPGA.

Another reason may be existing software. A huge body of code exists for the major DSP chip families, much of it already certified by independent standards bodies to comply with particular algorithms. A related point is that the DSP chip families have elaborate, mature code development environments, large libraries, and relatively large numbers of assembly-level programmers. With software in many designs creating 90 percent of the design costs, these points are not to be ignored, even for moderate-volume applications.

Nor is integration necessarily the least expensive approach, even in bill-of-materials terms. Sometimes an off-the-shelf DSP chip can simplify the logic design sufficiently to make a big difference in the cost of the companion FPGA or ASIC. This is particularly true if the application would benefit from floating-point computation. But floating-point DSP chips tend to be aimed at high-performance applications, not at cost- or power-constrained designs. That can make buying the DSP chip and supporting it with sufficiently fast memory a non-starter.

Analog Devices today introduced two new families in its floating-point SHARC architecture to address these concerns. Analog Devices senior product manager Satya Simha said that SHARC has found use in a wide range of higher-end applications, from typically compute-intensive military projects to professional audio, medical, and industrial uses.

OK, I have to take a moment out here to note one particular application in the professional audio market. According to marketing programs manager Denis Labrecque, along with studios’ move to 192 kHz multi-channel consoles, a big driver for SHARC in the audio world has been the explosion in computational demands to simulate, in the digital domain, the transfer functions of legacy tube audio gear. Go figure—dual 32-bit floating-point data paths and hardware filter and FFT engines to emulate a handful of vacuum tubes.

Anyhow, entering new markets outside the cost-insensitive military world has brought the SHARC architecture in contact with applications that require either lower system cost or lower power than the existing SHARC implementations could offer. Hence, the new families.

The new parts retain the SHARC core, which offers a dual-ALU 32-bit floating-point engine with independent address computation hardware. Outside the core, the new families also include the SHARC FIR, IIR, and FFT offload engine, which can run autonomous filter or transform calculations while the core is in use. There is also up to 5 Mbits of RAM and up to 4 Mbits of ROM available on various members of the families.

The low-cost 2148x family runs the core at up to 400 MHz. By exploiting the large internal memory to reduce the core’s dependence on external DRAM and peripherals, the designers were able to reduce the frequency of the I/O pins just enough to get the die working in a small QFP. That cuts the cost substantially compared to the ball-grid arrays used for the bigger SHARCs.

The 2147x family can use the same LQFPs, but the focus here is on reducing the operating power, according to Simha. He says the 2147x chips can keep their consumption down to about 360 mW in a typical use scenario, making them viable for larger battery-powered equipment, and very viable when heat is a problem. The design team cut the power in two ways: using an LP process variant to reduce static power, and extensive clock gating to cut dynamic power. The 2147x family chips max out at 266 MHz, and because of the LP process actually use a slightly higher core voltage—1.2V compared to 1.0V—than the 2148x family.

Both families use an SDRAM, rather than a DDR, interface to DRAM. This helps keep pin frequencies down for the QFPs, and it certainly eases board design. Also, it saves money. "DDR2 memory is cheaper if you are buying whole DIMMs," Simha remarked, "but if you are using individual DRAM chips, as many embedded designs do, SDRAM is cheaper."

By bringing the processing power of the SHARC core and its I/O subsystems to lower-cost and lower-power systems, Analog Devices hopes to spread the architecture from professional audio into automotive infotainment and home entertainment applications, and into the growing markets for portable and remote medical monitoring and diagnostic equipment, according to Labrecque. At the same time, the new families are changing the input parameters on the decision of whether you really want to implement your own floating-point DSP hardware in your next FPGA or SoC design.