Synopsys updates the HAPS ASIC prototyping system

As the size of the verification task for SoCs continues to balloon, more verification teams are turning to some sort of hardware emulation to increase the number of cycles they can run. But emulation brings its own hard decisions. Big-iron hardware emulators give nearly as much control and observability as simulation. But they are relatively slow and low in capacity, and they are beyond the budgets of most teams. FPGA prototypes—often on boards designed by the SoC team itself—are far less expensive, but they are design projects in their own right. They can be fast, even real-time, but they tend to offer little control or visibility beyond breakpoints and hooks you put into the RTL yourself with a resynthesis and remapping. And in practice, many design managers say it is a struggle to keep the design of a block in the FPGA congruent with its design on the tape-out track.

Synopsys has for several years tried to arbitrage this dilemma with a prototyping system mid-way between the big-iron and the FPGA boards. The HAPS (for High-speed ASIC Prototyping System) product line offers a family of motherboards with one or more big Xilinx FPGAs, and the ability to plug several boards together to expand the system. The boards have a high-speed link—the Universal Multi-Resource Bus (UMRBus)—back to your host computer, wherein resides a plethora of software for system set-up and partitioning, initialization, control, and debug of RTL synthesized into the FPGAs. There are daughter cards to provide system resources common to SoC designs, such as ARM cores, DDR2 interfaces, USB 3.0, and an HDMI link.

Today Synopsys announced a significant update to the family. The occasion is the arrival of new boards carrying Virtex-6 FPGAs. But there is more to the story than just new silicon.

The new boards, the HAPS 61, 62, and 64, exploit the density of the Virtex-6 chips to offer emulation capacity from 5.5 to 18 Mgates per board, according to Synopsys vice president of marketing George Zafiropoulos. They will also be significantly faster than previous systems, running at from 25 to 75 MHz system clocks typically, with local peak speeds of 200 MHz possible. Zafiropoulos said this was about 30 percent faster than the previous Virtex-5 boards.

Interestingly, according to director of marketing Larry Vivolo, the move from Virtex-5 to Virtex-6 contributed only about a 15 percent increase in system performance. Several other factors were just as significant.

One, Vivolo said, was a very thorough power and thermal analysis of the board, allowing the big FPGAs to operate at close to their design speed. Another factor was a new 40-layer board design full of balanced traces and signal-integrity tricks, which probably deserves an article in its own right. And, finding that with the new board the high-speed connector between boards had become a bottleneck, Synopsys designed their own connector.

There is important new functionality in the HAPS 6x family as well. One important point addresses the problem of maintaining system speed when a design must be partitioned between two or more FPGAs. "In one way, the Virtex-6 makes the partitioning problem for emulation harder," Vivola said. "The capacity of the FPGAs has grown much faster than their pin count. So there simply aren’t enough physical pins to interconnect blocks that end up on different FPGAs."

Synopsys attacks this problem with pin multiplexing. The partitioning software evaluates the signals that will have to pass between FPGAs. Based on the clock frequency of the originating block, the software assigns the signals to time slots on a set of 1 Gbit/s differential pairs that run between the chips. These are implemented in standard I/O pins in LVDS mode, apparently, rather than relying on the Virtex-6 fast SerDes resources. With multiplexing factors up to 128 signals per pair, this approach can increase the number of virtual pins between FPGAs by a factor of seven, while mostly preserving system performance.

A substantial speed-up of the UMRBus adds more capability, tying HAPS more closely into the Synopsys verification environment. By implementing an event-driven interface over the UMRBus, Synopsys has made it possible to run co-simulation between a VCS or other RTL simulator on the host and models in the HAPS. Similarly, the company has implemented a SCE-MI 2.0 interface over the UMRBus, allowing testbenches and behavioral models in C/C++, SystemC, etc. on the host to co-simulate at transaction-level with RTL running on HAPS.

Finally, Synopsys has offered a large set of its DesignWare IP models pre-tested for use on the new HAPS emulator. This will allow architects to quickly put together the industry-standard pieces of their SoC for emulation, even if they will back-fill later with IP from other sources.

With increased speed and capacity, co-simulation at RT and transaction levels, and a library of IP, Synopsys is hoping to attract more verification teams to HAPS, and of course to draw them, through HAPS, into the entire Synopsys environment. The HAPS-64 is in limited availability now, and all three boards are scheduled to be available by the end of 2010. They will never be as inexpensive as just picking up an FPGA prototyping board and some free software, but for design teams that can afford the difference they may well be a much better idea.