Aquantia's 40 nm quad 10GBASE-T PHY illustrates process, architectural and design-flow challenges of the new mixed-signal world

Aquantia this morning announced apparently the first quad 10GBASE-T PHY chip. While 10GBASE-T—10 Gbits/s over copper wire, albeit in specially-designed coaxial cable—is a significant achievement in itself, this chip design nicely illustrates several points about what life will be like for mixed-signal SoC design teams in the deep sub-micron world.

First, this is a 40-nm chip—and at that a very challenging mixed-signal design. How a relatively small design team managed to work at the leading edge of process technology is an interesting story in its own right. Second, the chip depends for its low power—quoted at 2 W per port when driving 10 m of cable—on a novel partitioning of functions between the analog and digital domains. Third, that partitioning, together with the very early process engagement, dictated an ambitious design flow.

According to Aquantia vice president of engineering Ramin Shirani, the company set out last year with test chips to verify the feasibility of putting four ports on one die. "It would mean grouping 16 high-speed pins on one side of the die," he explained. "We used test chips very early in the design to prove feasibility of the tight grouping and the power consumption targets."

"The project required multiple test chips with TSMC," added Phil Delansay, vice president of business development at Aquantia. "We were on the second 40 nm shuttle that TSMC ran. And we continued to use test chips to validate our simulation results."

This checking against silicon was particularly important, one suspects, because Aquantia engaged with 40 nm very early in the process development, before the models were entirely stable. This was particularly an issue with substrate-coupling models, which always seem to be the last to stabilize. The design team had to rely on its experience rather than just on modeling for this issue. "Layout for minimum substrate injection is very important," Shirani affirmed. "If you don’t understand it you have no chance to make your design work."

The architectural approach Aquantia chose is also interesting. Early on the designers concluded that the passive-network approach to echo cancellation used in 1GBASE-T would not be sufficient for 10G. But when they added the requirements for active echo-cancellation into all the other signal-processing tasks that go on in the PHY, they realized that the required level of digital signal processing would be outside their power budget. So they took a radical step. "We chose to implement analog circuits for echo cancellation, shaping, and equalization," Shirani said. "That meant we had a pretty sophisticated analog block sitting in front of the A/D converter. But it also meant a significant reduction in power." The savings came both because the analog functions are inherently lower in power than their digital counterparts, and because putting the analog functions before the ADC allowed the design team to use lower resolution and fewer taps on the digital signal processor.

Using these analog functions also meant that the design was now decidedly mixed-signal, with some closed-loop functions including both analog and digital signal paths. This profoundly influenced the design flow.

Shirani said that the team began simulation at the behavioral level with Simulink, translating the individual functions from Simulink models into models for Spectre during the implementation. "We have a lot of pride in our multi-mode design methodology," Shirani said. "Every loop was validated in multi-mode simulation before tape-out."

The problem with that level of thoroughness is time. If you model everything at the transistor level and run a flat simulation, you will be there forever. Aquantia started its functional models in Simulink, but during implementation every block acquired both a Verilog-A and a transistor-level model. This made it possible to run closed-loop, mixed-mode simulations of mixed-signal loops. But closed-loop simulations are notorious for not converging quickly. "Running the full clock/date recovery block requires about 25 days," Shirani said.

Hence it was vital for the team to understand what level of abstraction was necessary for each block in a loop for each experiment. And it was necessary to know where to look–in both the circuit topology and the time domain–for the answers to specific questions. "You must identify the critical points for simulation, so you don’t end up running enormous amounts of simulation time," Shirani said. "Depending on the experiment, we set the resolution differently, for instance. Knowing how to do that without losing data comes from having an experienced team."

There has been a lot of discussion about the need for mixed-signal simulation as analog circuits become more and more digital. But Aquantia’s chip illustrates the same need for the opposite reason—power constraints are moving some signal-processing functions back from the digital to the analog domain, presenting design teams with closed loops that contain both analog and digital paths. This may be simulation’s greatest current challenge, and so far it takes not only good tools but deep experience to crack it.