Latest from DAC: ST and Media Tek manage media SoC designs (part 2)

This posting continues from Part 1.

Philippe Magarshack, vice president of Central R/D at ST Microelectronics, took a more technology-oriented approach to describing ST’s management of a new multi-media SoC. He began by describing the technology environment: multiple power-gated regions, dynamic voltage-frequency scaling (DVFS), body bias to vary threshold voltage, and process, voltage, and temperature sensors on the die providing continuous monitoring and feedback of the chip’s state. Even with these powerful tools, Magarshack said, media SoCs present challenges.

One such is just figuring out how to estimate power. In early media SoCs, Magarshack related, there were only one or two probable use profiles. But as convergence turns a simple handset into a Web browser, messaging device, camera, 3D game console and GPS receiver, the number of possible use profiles multiplies until it is difficult to state which blocks of circuitry are likely to be active or passive at any given time. And without the use profiles, it is impossible to estimate the impact of any power-saving measure on energy consumption. Further, with leakage power coming under control with the existing industry tools, the focus was shifting back to dynamic power.

Another serious problem is power distribution—"a nightmare," Magarshack said, "with 9 separate power grids and either on-chip or off-chip regulators." And right behind power distribution was memory. "We had to completely redesign our on-chip memory architecture to meet power requirements."

The VP said that rather than relying on live application code and use profiles, the design team used the Dhrystone benchmark as a means of measuring memory power consumption. Magarshack then described the successive use of new EDA tools at various points to slash power dissipation in the clock trees—by avoiding excessively low clock skew, for example.

He said that looking into the future, ST would shift its focus once again, from dynamic power reduction at the RT level to energy savings at the system level. The company is looking both to Synfora for power-aware synthesis, and to Atrenta for ways of creating executable system-level models with power estimation.

Further, Magarshack said, ST is looking at three new technologies for dealing with the increasing problem of variations. For random variations, he said, ST will adopt statistical static timing techniques. To help deal with systematic, process-related variations, the company is building detailed lithography and CMP models to correct the values in their cell and interconnect models based on process variations. And ST seriously expects to move to restrictive layouts by 32, or at the latest 22 nm. "We have one study that suggests that we can reduce pattern-dependent variations from 13 percent of nominal dimension to zero by use of regular patterns in place of least-area layouts," Magarshack said.

While the ST executive discussed primarily technical issues, Andrew Chang, vice president of design technology at Taiwanese fabless giant Media Tek, focused on the challenges in design resources as the company undertook a 65 nm, 5-million-instance SoC. He described the chip as containing a 500 MHz CPU, memories operating at 300 MHz, and an hierarchical organization comprising eight top-level blocks.

Quantifying the drain on resources, Chang said that the next chip of this size could cost $60 million US to design. This design required over 200 engineers. And mistakes can make that bill run even higher: Chang raised some eyebrows by saying that the full cost of a two-metal-layer engineering change order could be as high as the cost of a full mask set.

Chang said that because of such design cost increases, even successful products won’t bail out an inefficient design team. "You may discover that volumes are increasing, but they are increasing faster than revenue," he warned. Chang prescribed a systematic drive to increase company efficiency, starting with a comprehensive life-cycle management flow for each product.

Focusing in on engineering productivity, Chang identified a number of organizational issues. Many of them stemmed from the inability of the design team to have a single, golden view of the design at the beginning of the project, and derive future views of the design from that one source. "There must be one data truth," Chang said. In part, this was because the rapid growth of design teams could overrun the reach of earlier, simpler management practices.

The need for coherence led Media Tek to adopt a strictly hierarchical design flow, Chang said, beginning with First Encounter and driving down to lower levels of abstraction within the blocks. When a block reaches implementation, it either achieves timing closure based on the requirements dictated at the beginning of the project, or the team iterates on the implementation.

Already at 65 nm Media Tek is using some DfM tools, Chang reported. "We are doing via doubling, wire spreading, and litho analysis at this time." He then went on to describe nine initiatives that the company has taken to improve engineering productivity. These included a single source for design data, increased reuse of internal IP, increased use of collaboration, and a number of measures to improve tracking of design data and goals during the flow.

Taken together these three pictures—one of team management, one of technology decisions, and one of resource and methodology choices—give a fascinating and challenging picture of low-power design at 65 nm and below. Designs are succeeding, but no one should take the problems lightly.