Actel SmartFusion blends FPGA, programmable analog, and an ARM MCU

The FPGA graveyard is littered with the last resting places of chips that combined programmable logic with a hard-wired CPU. The cause of death most often was imbalance: it was hardly every possible to get just the right mix of CPU performance, memory size, peripherals, and logic capacity to please more than a few customers. The interface between CPU and logic fabric was always problematic as well. Simple enough to explain to users often meant too slow; fast enough to attach a coprocessor often meant numbingly complex. Worse, the integrated FPGAs always ended up costing more than the discrete chips they replaced.

But Moore’s Law has a way of rolling over dilemmas. If you have a fast, dense, Flash-based process, in principle you could give most customers a superset of what their particular application requires—fast enough, enough memory, all the peripherals, and enough logic cells—at a total cost of ownership competitive with the handful of chips it would take to do the same work. Add in a flexible configurable analog section, and you might have a pretty persuasive argument. That’s a thumbnail description of Actel’s SmartFusion.

The SmartFusion chips comprise three main sections: an FPGA, an MCU, and an analog section. Exploring the FPGA first, members of the family offer from 60K to 500K equivalent gates, whatever that figure might mean. A more concrete measure of logic capacity is that the family offers from 1536 up to 11,520 flipflops. There are up to 128 programmable digital I/Os and from 32 to 96 Kbits (approximately) of block RAM. The fabric can implement designs with up to 350 MHz system clocks, Actel says. The programming technology is Actel’s unique Flash process, so it’s compact, low-power, and both non-volatile and field-configurable.

The microcontroller section centers on a 100 MHz ARM Cortex M3 core with the usual complement of advanced MCU peripherals, up to 512 KBytes of Flash code store, and up to 64 KBytes of SRAM, separate from the block RAM in the FPGA section. In addition there is a single 10/100 Ethernet MAC on most of the chips in the family.

The analog section is a little harder to sketch quickly. If you are familiar with earlier Actel Fusion chips, this analog section will be familiar too. It includes 12-bit, 600 Ksample/s successive-approximation ADCs and 12-bit sigma-delta DACs (up to three of each), up to ten 50ns comparators, and a variety of current, voltage, and temperature monitors. Altogether the chips offer up to 32 analog inputs and three outputs. One of the benefits of the Flash process, Actel points out, is that it gives you the high-voltage transistors you need for simple analog design.

Another interesting feature of the analog section is a dedicated 8-bit MCU Actel calls the Analog Compute Engine. Actel senior product marketing manager Rajiv Nema says that users program the ACE through a GUI, and the core in turn sets up parameters of the analog section such as sample rates on the converters, collects data from the ADCs, and drives the DACs. The ACE also serves as the interface between the analog section an the rest of the chip.

The FPGA, MCU, and analog sections are joined through a conventional AMBA AHB structure. The AHB matrix connects directly into the FPGA fabric, giving plenty of bandwidth for accelerators or low-latency digital preprocessing engines. This becomes particularly important, for example, in Actel’s motor control reference design, where slower control loops, with latencies longer then 10 µs goes through the MCU peripherals and is handled in software, and loops faster than that go through dedicated hardware in the FPGA fabric.

The AHB reaches the MCU peripherals and the ACE through APB bridges. Thus all the resources of the chip are bound together through familiar ARM interconnect technology.

The other critical component of such an SoC is the development environment. Actel offers software development through third-party development environments such as Keil, IAR, and SoftConsole. RTL development goes through Actel’s Libero environment. A third tool, Actel’s MSS Configurator, allows you to configure the MCU and the analog sections.

The SmartFusion family won’t be the answer to all mixed-signal control and sensor-processing applications. But if the application requires more processing power than you can get from a soft ARM core, can live with the modest analog performance, and can benefit from a substantial FPGA fabric, the chip family could be quite flexible. In fact the ability to pack a lot of logic, a substantial MCU, and a capable kit of analog blocks into a moderately-priced chip may mean that SmartFusion’s destiny will be quite different than the doom that overtook previous hard-MCU/FPGA integrations.