TSMC sign-off flows and reference designs: helping customers and treading on toes?

TSMC chose its San Jose Technology Symposium today to announce two rather significant initiatives for helping customers to complete successful chip designs. Both announcements are part of the Open Innovation Platform—TSMC’s catch-all of "what can we do to make you successful in a dreadful economic environment" programs. Aimed not at powerful early adopters but at mid-level design teams who bring more modest resources to a new process node, the two programs—one a fully-packaged turn-key design flow and the other a reference design for a critical analog block—will undeniably make it easier for these teams to get to market. But both initiatives will also tug TSMC further down the slippery slope towards picking winners and losers among EDA companies, and even openly competing against IP vendors.

The first program is what TSMC calls an Integrated Sign-Off Flow. This is a major step beyond the idea of a reference flow. It is a pre-packaged design flow for TSMC’s 65 nm digital CMOS. Pre-packaged, in this case, means not only do you get a PDK and a list of compatible tools; you get all the necessary libraries, IP views, technical files, scripts for selecting and installing the correct version of each specific tool in the flow, scripts for setting up the tool parameters and switches, and even a script for doing sign-off. This is, in deputy director of design services Tom Quan’s words, literally an automated, executable design flow. About the only thing you have to bring to the party is your own RTL and any IP not available from TSMC’s libraries. "You can actually have this flow up and running in your shop in a matter of days," Quan said.

The flow includes specific selections of vendor EDA tools, including a mostly-Synopsys set of place and route tools, mostly Mentor Calibre back-end and analysis tools, Apache RedHawk IR-drop and electromigration analysis, and the option of using Azuro clock-tree tools. It’s up to the customer to obtain the licenses for the correct versions of the tools from the individual tool vendors—as of now—but the scripts will do the set-up. "We are looking at other options to smooth this part of the process," Quan said. When it’s all assembled, the flow is essentially a version of TSMC’s 65 nm Reference Flow A, with the low-power option.

Quan said that this flow was a particular solution to a particular design problem. There will be other flows for other nodes, and possibly for other types of design such as analog/mixed-signal, as resources allow. And, with front-end design having more and more impact over critical issues such as DfM and physical closure, TSMC is also looking closely at the possibility of pre-packaged front-end flows. "We would probably start out with a reference flow in this area, and then move to an integrated sign-off flow later," Quan conjectured. "I can say that we have definitely been looking at just how early DfM needs to be introduced into the flow."

The second initiative takes the same concept—help the mid-range customer—in a quite different direction. The Mixed-Signal/RF Design Kit is both what its name implies and a great deal more. In effect, it is a full, silicon-validated reference design for a critical mixed-signal block, complete with the 65 nm RF-process design kit, models, and the Release Note specifying the necessary tool versions and settings to implement the design. Remarkably, the package includes a video and a set of step-by-step tutorials that, using the supplied IP as a case study, walk the user through the analog back-end design process.

The IP in question is no trivial example: it is a 2.4 GHz, fractional-N PLL synthesizer developed by Cadence in conjunction with TSMC, according to Cadence design flow architect Bob Mullen. The IP is provided in a range of simulatable views from behavioral level to transistor layouts. The views are designed to work with a primarily-Cadence design flow that includes simulation at several levels, extraction and analysis, silicon correlation data, and frequency-domain analysis. "This block is pretty much the proof point for a 2.4 GHz wireless design," Quan added.

Mullen said that the history of the synthesizer was fairly interesting. "This was originally a 180 nm design that we adapted to 65 nm," he said. The modeling approach is also interesting, including use of both behavioral-level models that include parasitics and table-driven transistor-level models from Spectre-RF. There is even some C-level system modeling, Mullen said.

And the synthesizer is just the beginning. Quan said that there will be other critical blocks that help illustrate the use of other flows, including some blocks in 90 nm and possibly in 40 nm as that process becomes more mainstream. Other tools will likely be added as well, including substrate modeling and power analysis—both particularly thorny problems for analog design. Again, the IP will be chosen for not only its usefulness in a design, but its ability to illustrate the use of a particular flow.

The Integrated Sign-Off design flow will enter limited distribution in Q2, with general availability in Q3. There will be no charge to TSMC customers for the download, but obviously customers will still have to license the individual tools from their vendors. The PLL IP and its kit is available now to existing contract customers, and will go to general release in Q3. It, too, is free to customers.

Both of these moves are certain to be a big help for teams just biting off 65 nm. But they also raise some eyebrows in the industry. One immediate concern, which TSMC sources admit has already raised some objections in the EDA community, is that by offering a single turn-key flow TSMC necessarily has to choose—and, implicitly, to recommend—particular EDA tools for a particular node and set of process variants. TSMC senior director of design infrastructure marketing Shauh-Teh Juang said that the company will do everything it can to be fair about this process, trying to include as many vendors as possible in the different flows it plans to release. And leading-edge designers will use these flows as a reference, not as a cast-iron flow, Juang argued. The customers who will use the flows without modification will be those who need the most help in getting their flow up and running. Of course, these customers may also make up the heart of the market for the EDA vendors, volume-wise, so there is much at stake here.

Similarly, TSMC’s ambitious program to create reference IP blocks has the potential to make particularly smaller, specialty IP vendors very nervous. The PLL, for instance, is there only to serve as a study model for using the AMS-RF flow, not to be used as a piece of production IP. "Designers would have to modify it for use in almost any specific application," Juang explained. But none the less, if the IP is there, for free, it certainly cuts into the appeal of licensing a similar Fractional-N synthesizer from an independent IP vendor, especially after you’ve walked through the process of taking the free reference design all the way to sign-off. As TSMC adds more IP blocks to illustrate more designs, it could seriously cut into the business of some IP vendors.

That may not be the worst headache for the IP community. Juang mentioned that TSMC is also considering full-chip reference designs for devices such as a SmartCard, an RFID chip, and so on. These would be fully manufacturable designs on which you could sign-off and order wafers. "These designs will be linked to particular process variants. For instance, an RFID chip would be ideal for showing how to use the flow for our low-voltage process," Juang said.

There doesn’t appear to be any intent for TSMC to intervene in the markets for EDA tools, IP, or chip reference designs. The company seems to sincerely believe that it benefits from open competition in each of these areas. But at the same time, TSMC must arbitrate between its desire not to interfere in the markets upon which it depends and its mandate to get its customers into production as quickly as possible. What TSMC executives see as the best trade-off point in this thorny decision may not be the point of greatest comfort for the suppliers impacted by the choices.