AMD and Virage Logic try a new model for third-party IP

An innocuous-looking announcement on the wires this morning from AMD and Virage Logic didn’t sound like much. But it may be the sound of the curtain coming up on a whole new business model for the third-party intellectual property (IP) business—and none too soon.

Virage and AMD announced that the two companies would collaborate on development of silicon IP, including some specific interface cores now and unspecified new cores in the future. The cores currently being productized are a gen-2 PCI-Express interface, an HDMI/DisplayPort interface, and a MIPI core. All three are to be available in both 65 nm and 40 nm versions.

So far it doesn’t sound like a big deal. But stay with me for a little background, and then an observation, if you will, of why it might be the beginning of a big deal. The three interface cores were developed for internal use by the graphics division of AMD, the former ATI. They were designed for standard bulk CMOS, not for the processor division’s more esoteric SoI process. And all three have been proven not only in silicon but in-systems at 40 nm by AMD. Virage intends to pick up the cores as-is and prepare them for commercialization as for-sale third-party IP, and then to market them.

Now Virage and the AMD graphics folks have a long history. Virage, one of the leaders in logic cell libraries, embedded RAM compilers and, more recently, in interface IP, has supplied the AMD designers for years. Neither the former ATI nor any other part of AMD has a history in the IP business. So why now does the IP vendor want to license IP from its customer?

The cynic might suggest part of the answer is that AMD needs all the revenue sources it can find right now, and that it would commercialize its employee lunchroom if it could figure out a business model. But Brani Buric, Virage’s executive vice president of marketing and sales, says there’s more to it than just a chance to cut a good deal for some interface cores.

Part of the equation, according to Buric, is time to market. AMD engages with its foundries on a new process node at about the same time that Virage begins developing logic libraries—very early. So a company like AMD will have complex interface cores, with their custom-design requirements and significant analog content, up and working much earlier than would normally be feasible for an interface IP vendor. Hence, if Virage can commercialize the cores quickly, it could get them to customers much earlier in the market window for a new node.

But there is another, possibly more important point. ATI’s interface development team, like that at many other large fabless companies, has built up a powerful heritage of system-level verification IP, design best-practices, and other learning that have a major impact on the robustness of their interface IP in real systems. By the time AMD says a piece of IP is ready, it has been run through skew lots, inserted in real SoCs, and extensively tested in actual systems with actual workloads, not just modeled in an FPGA or taped-out on a stand-alone test chip and rushed through a shuttle run. There are many steps in that process that make tangible contributions to IP quality. And those steps are not feasible for an IP company until they have already seen several tape-outs by customers. Virage can’t afford to design an SoC and integrate it into a range of systems in order to evaluate a new interface core.

So what it the interest here? It is that we may be seeing a reversal of roles for third-party IP companies. In the past, IP companies have generally been the IP creators. They have differentiated themselves by having more expertise in the specific function of an IP block than their customers did.

But as IP becomes more complex, maintaining that expertise on the slim margins of IP licenses is no longer feasible. It makes sense to suggest that as IP blocks get larger and more application-specific, IP vendors will have to depend on the first-tier systems-chip semiconductor companies to develop and verify the IP for them. The IP companies won’t have the expertise or the resources for the task.

As this shift takes place, the value-add of the IP vendors will change. No longer the domain experts for the IP, they will in stead add value by commercialization. Solid, correct IP needs to be cleansed of application-specific, flow-specific, and process-specific elements so that it is reusable. It needs to be parameterized so that it can be adapted to a wider variety of environments, from different system busses to different power-management schemes to different sizes and shapes. All these changes need to be verified. The IP needs to be documented to IP-industry standards (don’t get me started on that one …) and all the views that go into the IP design kit need to be created for all the tool flows the vendor supports. That in itself is a significant expertise, mostly application-independent.

This will probably mean a narrowing of net margins for IP companies yet again, as they have to license the cores themselves before they can commercialize and resell them. But if in fact a commercialization team can be pipelined to handle a wide range of cores efficiently, it means a reduction in what has been of late an alarming growth in the R/D cost of being a big IP provider. You don’t have to have a team of PCI-e gen-2 experts now, just good supplier relationships.

Like most supplier relationships in our world, these SoC-developer to IP vendor relationships will be more joint development partnerships than they will be traditional merchant-customer supply chains. Already, Buric says, Virage envisions having its own engineers involved much earlier in the development of the next generation of interface IP at AMD, in order to smooth out ahead of time the potentially treacherous path to commercialization, and to make sure the commercialization team has access to the right people at AMD. This evolution will undoubtedly influence the design of AMD’s cores, even the versions intended for internal use.

Even though it will require changes from both parties, the model has the potential to allow AMD to recapture more of its development costs on IP that could be useful on the outside. It has the potential to reduce R/D as a percentage of sales at Virage. And it could put higher-quality IP in the hands of Virage’s customers, increasing their likelihood of first-time silicon success and market success as well. It all seems worth exploring.