IMEC explores the 3D integrated circuit, one challenge at a time

The technology for 3D ICs is gradually maturing, according to a panel discussion at the IMEC Annual Research review Meeting in Leuven, Belgium earlier this week. Ubiquitous use of stacked and wire-bonded dice in cell phone handsets has made that particular kind of 3D assembly accessible to a wide range of designs. But there are more advances to be made in 3D integration, including replacing wire-bonding with flip-chip techniques—already common in some systems-in-package (SiPs)—and a thorough rethinking of the architectural implications of 3D. “The technology is basically there: 3D is a way out of the economic limits that are pressing on the growth of integration,” said Fred Roozeboom, a research fellow at NXP, during the panel discussion.

IMEC researchers see a straightforward path from today’s application of 3D packaging to what IMEC calls a 3DIC: a stack of radically thinned dice in which through-die vias and bump-to-pad connections make interconnect between dice almost a natural extension of on-die metal interconnect. The technology to go that far is coming, panelists said. Anisotropic etch, new side-wall deposition techniques and copper-nail deposition can now form through-wafer vias in the range of a few micrometers diameter, and IMEC is demonstrating the advanced wafer-thinning technology that can produce working dice only tens of micrometers thick.

But challenges remain. IMEC group science director Diederick Verkest offered the example of pulling all the SRAM instances out of an SoC and moving them to a separate die optimized for SRAM. A typical SoC today might require 10,000 vertical links between the dice to do this. That, in turn, could require via diameters on the order of 200nm to avoid disrupting the layout of the SoC. But IMEC science director Eric Beyne pointed out that not only do we not routinely make through-wafer vias that small, but the overlay accuracy we can achieve when stacking wafers is only about 1.5 microns—nowhere near enough to make sure that the vias would line up.

An even more serious limitation may lie in the architectural design rather than in the fabrication. Today most architects, if they consider 3D at all, tend to think in terms of functional clusters of dice from different processes and vendors: for example a logic die, a stack of DRAM dice, a stack of Flash dice, and maybe an RF die on the top. Such thinking is a long way from the sort of floorplanning based on inter-block traffic density, clock domains and power domains that these architects routinely do in 2D. Nor, if architects did think freely in 3D, would there be tool support for their thinking. “So far Zuken has been the only company to even show a roadmap,” panelist Jochen Reisinger, Infineon project head, commented.

Nor is this likely to change, since, several panelists agreed, the EDA industry won’t move on 3D until they see seats waiting to be licensed. In fact, the issue of motivation could make the move from SiP to 3DIC a very difficult step for many reasons.

Foundries are even less motivated than EDA vendors to get out in front of the 3DIC technology curve. 3D frees chip designers from the tyranny of the next node, allowing them to use more mature processes—and cheaper foundries. For IP developers 3D is just another huge headache with no standards to limit the scope of their work. Fabless semiconductor companies see 3D as a means by which they could lose control of the integration process, reducing their influence on the design.

The only party with real incentive is the system OEM. Unfortunately, today only a few system OEMs have enough influence over the design of the chips they use to impose a 3D solution on their partners. So the 3DIC is likely to emerge—if it emerges at all—first from the few remaining IDMs, in which the interests of the system developer and the chip developer coincide.