Everspin MRAM reaches 16 Mbits, looks toward embedded use in SoCs

Advanced non-volatile memory technologies form one of those topics like religion, politics, and child-raising: best not discussed at family get-togethers. Each of the various technologies—phase-change, magneto-resistive, ferro-electric, carbon nanowire, or whatever—has its own fierce partisans. And the whole sector has its skeptics. But while the debate rages over which technology is going to obsolete SRAM, displace DRAM, and frighten Flash, individual vendors are in fact winning sockets in niche applications.

One example of this progress is Everspin Technologies, the MRAM spin-off (sorry) from Freescale Semiconductor. The company today announced its first 1M-by-16 device. The part is designed to be pin- and function-compatible with a 35ns 1M-by-16 async SRAM, except of course that it is non-volatile.

There are points prospective users of the chip need to keep in mind. One is the power characteristics. Overall, the power consumption is similar to that of a 16 Mb SRAM, according to Everspin vice president of sales and marketing Doug Mitchell. But the write current is large—about 60-70 mA. In exchange, standby power is miniscule. The memory array requires no power for data retention, so the static current is simply the leakage in the peripheral circuitry.

In the short term, Everspin is pursuing sockets where the technology’s essentially infinite retention time, infinite endurance, and very high resistance to single-event upset are advantages. These include embedded designs that must operate at high altitudes or must respond to power interruptions without loss of state. Engine controllers in heavy equipment—where unintended acceleration is discouraged—and write journals in RAID controllers are examples.

In the longer term, Mitchell says, Everspin has three strategic foci: increasingly dense stand-alone NV SRAM chips, embedded memory in SoCs, and a bit of a side-line: magnetic-field sensors to replace flux gates in compasses.

The first two of these areas require a quick discussion of how MRAM is built. The bit cell comprises an array transistor and a storage element, much like a DRAM cell. But in this case the storage element is not a capacitor, but a resistor formed from two layers of non-ferrous magnetic films. The lower layer acts as a permanent magnet, and the upper layer as a reversible magnet whose polarity can be flipped by the programming current. Between the two is a tunneling layer, whose resistance is a function of whether the two magnetic layers have like or opposite polarity.

A potentially very interesting point is that the magneto-resistive element is built entirely on top of the interconnect stack, in a non-invasive, low-temperature, back-end-of-line process. So in principle, Everspin can put MRAM arrays on a standard CMOS microcontroller or SoC simply by giving the chip designers the specifications for the diffused transistor array, and fabricating the magneto-resistive elements on top of the completed wafers.

Today Everspin contracts for completed CMOS wafers and then fabricates the magneto-resistive layers on their own 200mm line in a shared portion of a Freescale fab. The only problem with this arrangement is that Everspin’s 200mm equipment can’t handle the 300mm wafers used in advanced CMOS fabs. So today Everspin is restricted to doing relatively low-density SRAM-like chips of their own design, and adding MRAM to microcontrollers built in mature processes.

That is unfortunate. Mitchell says the magneto-resistive element scales quite well to much smaller geometries. So there is the potential here for instances of very dense, moderate-speed, non-volatile RAM embedded in SoCs, with essentially zero standby power. That could get the interest of architects in a number of areas.