IMEC’s DRAM program will explore transistor, capacitor limits

As mentioned in a previous post, the Flemish Interuniversity Microelectronics Consortium, IMEC, has decided to include the interests of DRAM and non-volatile memory designers in their 32nm half-pitch front-end-of-line (FEoL) research program. This means that IMEC and industry researchers will work together to explore the apparent roadblocks to extending current DRAM and Flash technologies to the 32nm half-pitch node.

Specifically, the research program will explore three critical areas in materials science and device design for the DRAM community: the transistor to be used in the periphery of the memory chip, the transistor to be used in the memory array itself, and the all-important storage capacitor used in each memory cell. Not coincidentally, since Hynix is a partner in the research, these areas line up exactly with the areas of concern described by Hynix R/D vice president Sungjoo Hong at a recent IEEE symposium on advanced memory technology.

In some ways, the new research goals line up as well with the work IMEC had already planned for device scaling of logic processes. In other ways, the DRAM effort will be quite different.

The first area, the peripheral transistor, is one of the areas of overlap. IMEC director of FEoL integration Serge Biesemans describes the problem of developing a sufficiently fast peripheral transistor as a matter of integrating a viable 32nm logic transistor into the DRAM process. Unfortunately, that is no small matter. Today’s logic transistors, especially at 45nm and below, are complex masterpieces of nanoarchitecture, not at all the simple arrangements implied by the now-deceptive name Metal-Oxide-Semiconductor. The once-simple transistor may have a poly gate or, more likely, a metal gate. There may be two different metals involved to produce the N- and P-channel devices. There will likely be a high-k gate dielectric material of some sort, and a complex superstructure of new materials over and possibly beneath the transistor to induce mechanical strain. All of these materials and steps have to be introduced into a delicate process that lives or dies by high yields and short cycle times.

But compared to the capacitor problem, the peripheral transistor is easy. Because of the vanishingly small area allowed for each memory cell at 32nm, new electrode and dielectric materials will be needed to achieve sufficient capacitance in the gigantically tall cylinders that stacked capacitors have become. The metal will more than likely be Titanium-Nitride or something even more exotic. The dielectric will be a multi-layer film with many different components. The high-aspect-ratio cylinders will be held in place at the top by a fabricated mesh to keep them from falling over. Significant challenges, beyond the choice of materials and process integration, include achieving uniform dielectric deposition in thicknesses at or below 5 Angstroms. IMEC intends to do their research on planar capacitors, not on the tall cylinders or on Qimonda’s preferred trench capacitors, in order to avoid having the materials problems compounded by the mechanical ones.

Which brings us to the cell transistor. Today Samsung is already using a recessed-channel array transistor (RCAT) which is a kind of 3D structure, to artificially lengthen the channel and reduce leakage. But it seems clear that by 32nm the industry will have to move to finFETs. Biesemans explains that in the DRAM cell, transistor leakage translates directly into retention time, so it is a critical parameter. Only some sort of multigate device can control leakage sufficiently in the available space. The IMEC program will not have a separate project to develop a DRAM finFET, but rather will evaluate the multigate transistor being developed in the logic program as a candidate for use in the DRAM cell array.

Biesemans emphasizes that the point of the research is not to produce working cell designs or DRAMs. It is to explore the materials, device characteristics, and above all the process integration issues upon which the research partners will eventually build their DRAMs. Bringing its university and equipment-industry connections and the power of its long-standing logic-scaling research to bear, IMEC should be in a position to contribute.