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Representing analog circuits for optimization: an old debate

March 5, 2009

If you are going to analyze and optimize an analog circuit, you have to represent it in some form that makes analysis possible. And as the implementation gets more and more complex—because of tiny process geometries, huge variations and crummy transistors, for example—the choice of a medium for representing the design becomes a critical decision. But for as long as I can remember there has been a debate among designers over just what that form ought to be.

One camp I would call the intuitive school. These people—of whom I am in awe, by the way, much as I am in awe of a musician who can sight-read new material and play it on a woodwind—have an intuitive grasp of how a circuit will behave, just from looking at the schematic and the device sizing data. They can often get so clear a picture of the circuit behavior in this way that they can do sensitivity analysis and optimization by a few recursive estimates. But I understand that this technique is getting harder as geometries shrink.

Another camp I would call the computer faithful. These people learned analog design in the days when SPICE was the new wonder-tool, and they actually seem to think of circuits not as physical entities, but as SPICE models. It’s just that the physical embodiments are much harder to modify than the models. In this case, analysis and optimization seem to be a matter of lots of SPICE runs coupled with ingenious experiment design and clever sampling techniques to avoid a full Monte-Carlo analysis.

Finally, there are the mathematicians. I have a certain sympathy for this school, since the only things I learned about analog design at university were in automatic controls and systems synthesis courses, where circuits were not things, they were transfer functions in the log(s) plane. Or, across the campus in another building, they were linear differential equations that could be solved either analytically or on an analog computer. (No, we did not use a steam-driven generator to power the computer. Stop that.)

For the most part, analog designers I have met in industry seem to fit into one of the first two stereotypes. But there has been one notable exception. The folks, such as Mar Hershenson, who started Barcelona Design were very much of the mathematical school. Their initial concept at Barcelona was that if you modeled an entire class of analog circuits with similar functionality as a set of equations, you could apply formal optimization techniques to the equations and produce a highly-tuned implementation of the circuit to fit any set of constraints you wished.

According to Hershenson, this actually worked quite well. But deriving the equations from a base circuit topology was a very specialized task, and so it turned out that Barcelona had to do the base designs for you, and then let you do the optimization. That was just the opposite from the way most designers—especially the intuitives—wanted to work. They wanted to define the circuit, and let Barcelona’s tool do the optimization. So Barcelona went away.

But the idea—and much of the team’s core–survived, and reappeared in the form of Sabio Labs. This time the idea was to extract the mathematical expression from the customer’s design, and then use the mathematics to perform optimizations. This worked well enough that Magma bought the company in April of 2008, and integrated the Sabio tool into the Titan analog/mixed-signal design environment.

In its integrated form, the tool can extract a process-independent mathematical representation—based on, but not exactly like, the Matlab format—from either a schematic or a GDSII layout automatically. The tool also takes in a design-requirements file that captures constraints not deducible from the design data. It also absorbs process models for the target process, and produces an optimized design in the target process.

Hershenson says that the use of a process-independent mathematical representation of the design has a number of benefits. For one, it allows analytical optimization of the design rather than trial-and-error. For another, the models at this level are fast enough to analyze that designers can use them to explore the solution space, not just to drill down on one idea. And also, Hershenson—ever the mathematician—says that having a mathematical representation gives designers another independent way of looking at the design. Often reality checks and tests of simple assertions are easy in the mathematics even after they have become very difficult at an intuitive level.

The three design styles live on. I wouldn’t expect any skilled analog designer to convert from one style to another. They seem to be as innate as left- or right-handedness. But it does appear that as we move deeper into the realm of the sub-65nm, mathematics may reassert itself as a valuable—if not as the only viable—way of looking at complex analog designs.

Posted by Ron Wilson on March 5, 2009 | Comments (11)

March 18, 2009
In response to: Representing analog circuits for optimization: an old debate
fromExperience commented:

From what I've seen, analog designers, especially the most experienced, don't tend to be interested in tools which improve the time to market of their designs, or performance or yield. Whether it's due to pride or overall lack of objectivity, they don't tend to focus on the overall positive result. This has killed the adoption of these new methods. They have all been in existence since the early 1990's. They are repackaged in many forms, but whether they are local or global optimization methods, my opinion is that the lack of teams dedicated to this purpose solely to compliment the role of the analog designers, has kept this market from growing. It's evident from the fact that though EDA companies have picked up the companies which show some promise, the penetration is relatively weak. These tools work, but they are in conflict with the motivation of analog designers role in guaranteeing fast TO's of robust circuits. There needs to be a team who's role is to concurrently execute DFM/DFY(call it what you want) optimization on top of the analog designers charter.


March 17, 2009
In response to: Representing analog circuits for optimization: an old debate
Brad Wood commented:

Thanks for that Middlebrook link---it''''s an interesting bit of work. Inriguing problem as to how to program automata to perform such "entropy reduction".


March 13, 2009
In response to: Representing analog circuits for optimization: an old debate
Philip Oakley commented:

An intersting viewpoint on analysis is give at www.rdmiddlebrook.com/D_OA_Rules&Tools/index.asp where Dr Middlebrook highlights the ''entropy'' of various forms of equation. The discussion shows that there are different approaches to what constitutes information entropy. Good maths counts...


March 12, 2009
In response to: Representing analog circuits for optimization: an old debate
acnvrt commented:

aice, just read Ron''s article on Solido. He poses an interesting question - But there doesn''t yet seem to be any such debate between corner-based and statistical analyses in the analog world, at least in public. Whether application-parameter-based corners will be sufficient, or whether they will be a stepping-stone to a full statistical analysis of analog circuits. Using application based corners sounds interesting. Does anyone have some thoughts on this?


March 11, 2009
In response to: Representing analog circuits for optimization: an old debate
chillin commented:

Monte-Carlo is deemed too CPU-intensive, but this is only true if you use a straightforward simulator-in-the-loop approach. (Pseudo-)Monte can become practically feasible if simplified but accurate enough models are used (e.g. PDF solutions, ExtremeDA). MunEDA's approach is a mathematically sound one, taking the full circuit description into account, but it could be used just as well with a reduced model to speed up run time. However, their approach cannot beat Monte Carlo simulation based approaches in general.


March 10, 2009
In response to: Representing analog circuits for optimization: an old debate
aice commented:

swka, here's a review Ron did of Solido: www.edn.com/blog/1690000169/post/180040818.html


March 10, 2009
In response to: Representing analog circuits for optimization: an old debate
swka commented:

Ron, good analysis on the state of minds on analog optimization. I think Chillin is right on point with the observation that it is all the manual work needed to get the tool to start to generate reasonable results along the right direction. I might add, however, such mathematical representation is like extracting deign intend from schematic, and if there is a way to do this with enough accuracy, it could serve as basis for the holy grail of analog topological synthesis. I am curious to hear your comments on other analog synthesis companies, like Solido and MunEDA.


March 10, 2009
In response to: Representing analog circuits for optimization: an old debate
chillin commented:

Analog/MS ciruits typically behave strongly nonlinearly in the tunable parameters. So using only transfer functions to optimize generic analog circuits is infeasible. The catch in Sabio's approach is "The tool also takes in a design-requirements file that captures constraints not deducible from the design data". This is actually where automation is toughest and if the amount of effort the designer has to put into this step is limited, it's a critical usability and selling point. The rest can be done automatically, either as part of the design process or during library characterization/generation. It's like expert-system-based analog design. As long as updating the expert system's knowledge is a substantially smaller effort than manually optimizing the actual circuit, it makes sense to go for the (semi-)automatic approach. This is likely to be true for automatically optimizing *families* of similar analog circuits. A topic that has not been mentioned here is that the quality of analog/MS circuits with new process nodes is completely dependent on the quality of the libraries, and typically these have a larger error margin for analog in the beginning of the process roll-out. So a very valuable piece of design information would be the ability to have these (or any other interesting margin) propagated through the circuit and see them as error margins around any objective and constraint value that is of interest. Here a more efficient description of the circuit is very useful; instead of running many circuit simulations (with too high accuracy) the abstracted mathematical representation can generate results much faster.


March 9, 2009
In response to: Representing analog circuits for optimization: an old debate
Mouse commented:

In one way that is inline [in computational world, every functionality has to be algorithmic] some algorithmic steps can utilize mathematical representation. Always remember - it is never like math-represents-the-real-world; rather exactly opposite, and always like make some mathematical model, that somehow ACAP [= As Close As Possible] fit-the-real. Let's talk about accuracy :: Thinking from the other side it is going exactly opposite to how a real sub-wavelength device can be mathematically modeled falls close to the Heisenberg's uncertainty. At micro level, as per quantum mechanics, the so called silicon lattice band structure, with defined dose of impurities at 22nm MOS channel, has multidimensional variability issue. For every precise atomic change in the lattice structure of the challel, and its neighborhood, a new mathematical representation of the channel will be necessary, that limits the raw applicability in Analog. Let's talk about Representing Analog circuit - what circuit? - say for example - the whole PLL Yes. A completely new approach of circuit design needs to be evoluted - in which the overall circuit-characteristics will not change even if couple of device works within 40% variation from intended behavior - might be mathematically possible [with exceptions]. One school might come out with even smaller MOS, in which single surface-channels are heavily unpredictable. Now, increase predictability with multiple channel - tri-gate or finfet structure, even larger digital-core, with error-correction at a few bit level at various stages, and at the periphery work with A/D, D/A, conversion and achieve overall the desired alalog behavior. Analog optimization will end up with another universal limitation then - the maximal optiized implementation - if there exist at all, [for a defined transfer function] will utilize same Silicon-Area and will be process independent [to a certain extent].Because, when manufactured under lower node technologies will need more circuitry to compensate the inherent unpredictability issue, and with larger nodes lesser device, with lesser additional compensation [and |or] ECC circuitry overhead.. and so on..


March 9, 2009
In response to: Representing analog circuits for optimization: an old debate
anon commented:

Yes, agreed new techniques/tools needed for sub-65nm analog given the complexities that popup. Mathematical approach of Magma sounds promising. Seems like a market getting attention in EDA. New analog EDA tools for sub-65nm are also out from Cadence (Virtuoso GXL), Synopsys (Custom Designer), Solido (Variation Designer), Berkeley Design (AFS).


March 5, 2009
In response to: Representing analog circuits for optimization: an old debate
prince commented:

I agree with your view that mathematical analysis of circuit will play a key role in future design. More over as chips are getting faster every day, ability to explore fairly wide sample space in short duration is now a possibility.

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