Intel’s path to 45nm: why the big lead, and how? Restrictive design rules, perhaps?

There has been intense speculation in process engineering circles about just what Intel is doing in process development. The pitch on this guessing-game will increase as we get closer to this year’s IEDM conference, where the company is scheduled to give several papers on their 45nm process. But in the meantime, we should make some observations.

To start with, a few things are known. Intel appears to be further along toward production with a real 45nm process than anyone else. They also appear to be getting far better results, in terms of power-performance and yield, on 65nm than almost anyone else—certainly better than AMD, which rumor says is in serious trouble over 65nm yields and is not finding its way out.

We also know, from company statements, that Intel is not using immersion lithography even in critical layers at 65nm, although they are apparently, according to at least one report, using it at 45nm. (Note: this proved to be incorrect. See comments below. -ron) Assuming that Intel process developers are using the same physics as the rest of us, what the heck is going on?

The most plausible answer I’ve heard is that Intel attacked the 65nm and 45nm yield problem from a number of fronts simultaneously. Instead of trying to find a level of OPC that would produce perfect arbitrary shapes, they optimized the complex surface of lithographic techniques, OPC techniques, and circuit tolerances to give them working silicon for the minimum equipment cost, loss of throughput and elaborateness of decoration. This seems to have resulted in a choice of strong phase-shifting, some carefully-chosen OPC techniques, and for most layers, dry lithography.

This is entirely in line with an argument put forward by Luminescent Technology’s new CEO, Moris Kori, that the ability to explore the entire solution space for local optima is vital to finding the right process decisions. Kori is of course arguing in favor of one of his products, which allows designers to feed information on mask technologies, optical columns, exposure techniques and illumination, OPC techniques into an exploration tool and compare simulated results for actual patterns. But his point stands independent of his financial interest.

But I don’t think that is the entire story. There is pretty good circumstantial evidence that Intel is also using one more degree of freedom, one that has been anathema to many designers: restrictive design rules. For example, in a January, 2007 paper here, Intel authors Farhang and Deeter said “Defining Robust (sometimes referred to as Restrictive) design rules (RDR) that mitigate the variability challenges is the foundation of our DFM strategy.”

Could this be a silver bullet to delaying immersion lithography, improving yield and reducing variability? Well, yes it could, if you in fact have your process engineers, your product engineers, your library development team and your custom circuit designers all in one organization, and if you are willing to impose sufficient discipline on them all. Given these criteria, the process Farhang and Deeter describe of co-optimizing the process, the development cycle and the product design can work.

If you use rules that restrict the number of patterns that can occur on a mask, you free lithography experts and process engineers from having to come up with a process that can do everything—they can concentrate on doing only the patterns that are allowed. Needless to say that is a huge reduction of the domain of the problem, and frees you from having to throw every technology you can get at the solution.

In the past, we have mainly heard discussions about whether nasty restrictive design rules—intrusions on freedom of expression—would eventually become necessary at some distant future process node. The consensus has been that they might, but they’d better not because designers would fight them. Now we are faced with the possibility that while we were debating personal freedom, Intel worked out that a severe restriction of the design space would have substantial advantages on today’s processes, and put that observation into practice. If that is the case, there is at least a marvelous irony in it.