ARM 1176 in IBM SoI process demonstrates a cell-based flow

For several years it has been clear that SoI processes have a more favorable speed vs. voltage characteristic than comparable-node bulk silicon processes. This advantage can mean either lower operating voltage at a given speed—and thus lower power—or higher performance at a given voltage. And the presence of vast quantities of both the Xbox 360 and the PlayStation-3 should eliminate any question about volume manufacture, at least from IBM. So why is SoI still so rarely used?

The normal answer is the lack of design infrastructure. Early on, most SoI designs were at the high-performance fringe, and so people rightly associated SoI with custom design and highly-skilled teams. It would require new device models, new libraries, and new tools to make SoI work in a normal cell-based RTL flow, this reasoning said.

But three papers at the IEEE International SoI Conference yesterday strongly suggest that the situation has changed. Jean-Luc Pelloie of ARM, Kevin Kranen of Synopsys, and Michael Jacobs of Cadence described implementation of a synthesizable ARM 1176 core with its associated memories and I/Os in IBMs 45nm SoI CMOS, using an off-the-shelf Synopsys-based standard flow. Pelloie’s paper described the design decisions and results, while Kranen’s and Jacobs’s papers—discussed in my next posting—described the flow and how it was possible to use standard tools.

The goal of the project was to demonstrate that a design team without SoI experience, using a standard flow, could implement a complex digital core from RTL, and to compare the results to those from a bulk CMOS design, Pelloie explained. The ARM researcher then briefly described the ARM 1176 configuration chosen for the test: the core, 32 Kbyte instruction and data caches, and the necessary I/Os for a functioning microprocessor. Target performance would be 500 MHz worst-case at 100 mW total power dissipation.

One of the early decisions was the exact choice of process point. Pelloie explained that the IBM 12s process offers four different threshold voltages and three core voltages. As this was to be a simple design flow, without use of multi-threshold or multi-voltage design techniques, the designers would choose only one threshold voltage and core supply voltage. Over the range available in the process, they estimated it would be possible to build anything from a very-low-leakage 200 KHz processor to a high-power 1.5 GHz core. Based on their 500 MHz goal, the designers chose a mid-level threshold voltage and a 0.81V core voltage. This point should allow up to 600 MHz operation while moderating leakage currents, according to process estimates.

The design flow was deliberately simple, Pelloie said: the key pieces were standard versions of Design Compiler, IC Compiler, PrimeTime, and Power Theater, all from Synopsys. The team used these standard tools with special libraries created for the 12s process. The standard-cell logic libraries and I/O libraries were developed at ARM, and the memory libraries came from IBM. It was the use of these libraries, and an adaptation of multi-corner optimization that allowed use of a standard flow.

Pelloie reported on the resulting die, and compared it against simulations of exactly the same design done in IBM’s 45LP bulk CMOS process, both evaluated at a typical process corner. The SoI die was 7.3 percent smaller than the bulk design, consistent with previous experiments that have yielded smaller dice for SoI designs. Using the Dhrystone technique to determine maximum operating frequency, the SoI core achieved 600 MHz at 0.81V. At 500 MHz dynamic power was 55 mW, while static power was a noticeable 9.3 mW.

In comparison, the bulk design required a 1.1V supply to reach 500 MHz, and dissipated 104 mW dynamic power at that speed, almost twice the dynamic power of the SoI die. But in contrast, the LP process had less than 2 percent of the leakage of the SoI design. Pelloie observed that in order to produce an SoI design with both 500 MHz performance and low static power, it would be necessary to use more aggressive leakage management techniques in the design flow.

A questioner asked Pelloie about the choice of transistor types for use in the design. The IBM process offers both body-contact transistors that behave essentially the same as bulk-CMOS transistors but require extra space, and floating-body MOSFETs that are compact and fast, but exhibit a history effect that makes their threshold voltage a function of the charge trapped under the channel, and hence dependent on previous switching history. Pelloie replied that the core logic cell libraries used only floating-body devices. The I/Os used some body-contact transistors. And the memory designs used floating-body transistors in the arrays, and body-contact transistors for some delicate functions such as sense amps.

This brought up another important limitation in interpreting the results. This was a purely digital design. Doing a 45nm analog design in SoI would still be a significantly different task than doing the same design in bulk CMOS, primarily because of the history effect in the floating-body transistors. Similarly, non-synthesizable hard IP is rarely available in SoI processes, so designers of a full SoC would still have to go into the design knowing exactly what they were getting into on the analog, mixed-signal, and power circuits. Yet this result stands as a clear proof of concept for implementing a digital IC in a standard flow, and realizing the benefits of SoI. It’s worth a look.