Leti integrates lasers with CMOS for monolithic optical interconnect

Along with all of the process, design, and verification issues we face in the next few years comes the really bad news: we are running out of both I/O and interconnect bandwidth to support the enormous processing densities we are creating. Local on-chip interconnect may not be an issue yet. But we really don’t know how to get enough bandwidth between the major blocks on a future-generation SoC. Nor can we get enough bandwidth onto and off of the die. Estimates suggest that we will be needing 100 Terabits/s both for on-chip networks and for interchip links.

But that kind of bandwidth is pretty much out of the question using electrical signaling: it will take optical communications, and probably dense wavelength-division multiplexing. And WDM, in turn, will require lasers, detectors, mux and demux structures, modulators, and waveguides to be integrated into CMOS chips.

Therein lies a challenge. Silicon makes pretty good waveguides. But its bandgap structure is wrong for lasers and detectors. And the materials that do make good lasers and detectors are mostly poisonous to CMOS processes.

There’s a lot of work going into this problem. Intel has demonstrated silicon optical circuits relying on external lasers, and Indium-Phosphide lasers as bonded structures on CMOS dice. And today the European research consortium Leti announced a similar result: that they have fabricated lasers in a multi-die stack, using a technique fully compatible with CMOS processing.

The technique starts with fabricating a CMOS wafer that contains the processors, memories, and other blocks of the system, along with silicon waveguides for block interconnect, according to Leti photonics program manager Laurent Fulbert. This is a vanilla CMOS wafer, processed normally. Next, the Leti researchers bond individual InP dice onto the top of the wafer’s interconnect stack, using low-temperature bonding. Finally, the researchers fabricate laser cavities in the InP die, aligned with the waveguides in the underlying silicon, and deposit electrodes formed in a Ti/TiN/AlCu stack. All of these metals are already used in CMOS wafer processes, so integration is not a challenge. The team did have to develop special handling procedures for processing the InP dice in the CMOS clean room, Fulbert said.

Today, the dice are placed on the wafer manually. "We are looking at doing this with a pick-and-place tool. The accuracy doesn’t have to be that great, because we align the laser structures with the waveguides as we fabricate them," Fulbert explained.

Fulbert said the process could build just about any configuration of solid-state laser in the InP die. But these experiments have used a horizontal microdisk laser. The microdisks transfer energy into the underlying waveguides through evanescent coupling, so there is no need to direct light from the InP die into the silicon. Fulbert said the team has not yet used this structure to carry data. But a similar device using different III-V materials has carried 4 GHz modulation. "This device should be at least as good," Fulbert predicted.

The research, part of the EU-funded Wavelength Division Multiplexed Photonic Layer on CMOS (WADIMOS) project, is also working on detectors: one project is using epitaxial Germanium on the CMOS, and another is using this die-bonding approach to put InGaAs dice on CMOS wafers.

There are still many questions, including the details of integrating this new back-end-of-line process into an advanced CMOS flow, and how the approach would work with a stacked-die CMOS assembly. And 4 GHz/channel is still a long way from 100 Tbits/s, even with dense WDM. But like the Intel work, this is a milestone.