When an ASIC vendor partners with an EDA vendor: a new model

An announcement of a new ASIC service from Open-Silicon today underlines an interesting idea that seems to be spreading in the ASIC world—buying, or otherwise partnering with, an EDA point-tool vendor to produce a new ASIC service. As the range of plausible exit strategies for EDA start-ups continues to narrow, such relationships may become more of a trend than a novelty. What the impact will be on the much-worried-over EDA infrastructure is not clear.

Open-Silicon’s new service is called MAX, and has three aspects: PowerMAX, CoreMAX, and VariMAX. Each of these design services optimizes a design for one particular variable: power dissipation, core performance, and robustness against variations, respectively. Each of these optimization programs is based on the conventional tools advanced design teams normally use for the purpose. In the case of power, for example, Open-Silicon uses techniques such as multi-threshold design, clock and power gating, and voltage islands in conjunction with a conventional power-aware back-end flow and TSMC’s PowerTrim service to scale channel lengths after layout.

But to this conventional foundation Open-Silicon has added proprietary capabilities: back-biasing, library recharacterization, and a unique capability to generate custom cells—such as fractional-drive cells or merged logic cells—on the fly. These capability come in part from Open-Silicon’s acquisition last year of EDA start-up Zenasis Technologies.

The Zenasis tool set allows Open-Silicon designers to create, on the fly and based on the design’s needs, additional cells that by construction match the cell library currently in use, and by construction are DRC- and DfM-clean. This capability, according to Open-Silicon director of marketing Colin Baldwin, can reduce power consumption at the chip level by as much as 20 percent. It can increase performance of a core by up to 8 or 10 percent. It is sufficiently effective, Baldwin said, that Open-Silicon has been approached by some outside chip design teams specifically to harden CPU cores for them, without engaging in a full chip design.

Typically, Baldwin said, the internal tool will generate something on the order of 100 additional cells in addition to the existing library elements. The tool inserts these cells in place of the standard ones in locations where its analysis indicates that a custom cell would make a difference. For example the tool might create a fractionally lower-drive cell to use in place of a standard cell in order to trade a little bit of timing slack for a little bit of power reduction. In any one location the improvement is incremental, but it adds up, both in reduced power and reduced path delay.

Another of the power-reduction capabilities here deserves note. Open-Silicon appears to be the first ASIC vendor to offer back-bias as a means of threshold control in an ASIC process. By biasing the well beneath the transistors, this technique can lower or raise the threshold voltage, allowing you to systematically compensate for wafer-to-wafer variations in threshold voltage, or to simply move the leakage-delay point for a given library. The reason this is practical in an ASIC service, Baldwin explained, is again the proprietary tool set: it allows library recharacterization at a different threshold voltage, temperature, or whatever, in about six to eight weeks. This, for example, makes it possible for Open-Silicon to offer leakage sign-off at customer-specified temperatures.

Similarly, Open-Silicon uses the tool set to perform logic optimizations via new cell types, reorganizations, and new placements on the fly to aid in performance enhancement. The impact on performance is not as dramatic as it is on power, Baldwin says. But a speed increase of 6-8 percent can dramatically shift the binning of a design. It can even allow the use of 8-track instead of 12-track libraries in some cases.

It is tempting to look at Open-Silicon’s purchase of an EDA company as a special case with interesting results. But another news item crossing the wires last week makes one wonder. Wipro NewLogic, which is a design-services company rather than an ASIC vendor, has teamed with analog circuit porting specialist IN2FAB to offer an analog design porting service. The object is to make chips with heavy analog content portable among several fabs from a single netlist. A different scenario, but again an interesting case in consolidation between a tool vendor and a larger organization, creating a new business path for a point tool vendor. We may be seeing more of this.