Yet another new idea for FPGAs: relays?

March has seen two significant announcements from FPGA start-ups with innovative architectures: Tabula, with their time-domain-multiplexed architecture, and TierLogic, implementing their routing switches in a layer of thin-film transistors. Both approaches promise to significantly reduce the die size and cost of high-end FPGAs. But before these announcements broke, a relatively unnoticed paper at February’s International Symposium on FPGAs described what may be the most radical technology of them all: FPGAs using electromechanical relays.

No, this is not an early April Fool’s joke, nor is it one of those "let’s see if anyone will publish this one" academic exercises. The paper presented work by professors and students at the Stanford University departments of electrical engineering and computer science, and researchers at Altera Corp. The work was supported in part by DARPA funding.

The paper describes a conventional FPGA fabric in which the SRAM cells and MOSFET passgates that control the interconnect routing are replaced by MEMS relays. The relays would be fabricated in an encapsulated layer between Metal-3 and Metal-4, according to Stanford professor Subhasish Mitra, so they would neither take up silicon real estate nor interfere with the critical routing on the first two metal layers.

Beside saving space, the MEMS relays have other potentially useful characteristics. By playing with the design, size, and materials you can change the voltages necessary to open and close the relay, the speed of the relay, and its ON-resistance, according to Roger Howe, Stanford professor of electrical engineering and faculty director of the Stanford Nanofabrication Facility. Fortunately for process integration, materials already used in CMOS fabrication, such as Aluminum and Titanium, also make quite acceptable relays. Fabrication does not require high temperatures, so it is possible to fabricate a layer of relays in between interconnect layers without disturbing the CMOS process.

Because these are nanoscale devices—the width of the relay’s moving beam may be the minimum dimension in the chip’s lithography—they behave quite differently from conventional relays. For instance, the MEMS relays are actuated by electrostatic, not magnetic, force. So the actuator does not draw current except to move the beam from one state to the other. And the devices have inherent hysteresis, so that after you close the relay it will stay closed until you significantly lower the actuator voltage—in other words, you can make latching relays that consume essentially zero static power. Further work on the design, Mitra said, could shift the hysteresis curve so that a positive voltage would latch the relay and only a negative voltage would release it—thus creating a non-volatile latching relay. The ON-current of the relays is a function of the size and materials, but is generally in the area of a few kOhms, quite consistent with the ON-resistance of today’s pass gates.

The paper explores simply substituting the latching relays for the SRAM cells and pass gates currently used in SRAM-configured FPGAs. There is also a discussion of reorganizing the SRAM-controlled multiplexers in the FPGA fabric and replacing them as well. In these applications the relays would carry signals across their contacts, so their ON-resistance would figure into signal timing. But the relays would only change state during programming, so their programming time and current would not impact the FPGA’s dynamic performance.

The paper claims that according to calculations, using the relays would result in a reduction of more than 40 percent in footprint on the die, over one-third reduction in static power, and reduction of over a quarter in critical-path delay. The team is currently working with a foundry to select the process for a test chip to begin confirming these figures.

Current and near-term research includes designing the underlying FPGA, selection a design for the relays, and working out an encapsulation technique. Howe said that the team is studying techniques for encapsulating the relays between interconnect layers, including microshells and the Cavendish Kinetics technology.

There is longer-term work to do as well. "We believe that to take full advantage of the MEMS relays would require a change in the FPGA architecture itself," said Jeff Watt, technology architect at Altera. Among other possibilities, Watt said, the relays could prove very suitable for implementing look-up tables, the fundamental building blocks of FPGA logic cells. And the overall organization of the FPGA—from logic cells to routing fabric—is today based on the assumption of pass-gate-and-buffer interconnect, and might come in for a thorough rethinking.

The work is not nearly as near-term as Tabula’s or even TierLogic’s: the team has not yet even selected a process for test chips, and there is no talk at this stage of productizing anything. But the work is a clear reminder that scaling will make the conventional SRAM-FPGA technology less and less viable, and, like DRAM designers, the architects of the FPGA world have to keep thinking about their alternatives.