When networks collide: Applied Micro explains the PQx

The demand for bandwidth across the global network is rapidly altering not just the capacity, but the underlying structure of the net. Legacy telecom SONET and enterprise Ethernet networks are retreating into isolated segments, perhaps destined to vanish. In their place, Carrier Ethernet is seizing the network edge and diffusing out toward the customer premises. OTN is reaching out from the network core, through Metro networks and into the edge. And so nearly every portion of the network is in transition.

That means opportunity for suppliers of networking hardware. There is a need for higher speed ports, obviously. But also, carriers need greater integration so that they can gang more ports in their quest for 100 and 120 Gbit/s line cards. And the carriers need flexibility, so that they can use the same basic hardware with different physical media and protocols as their networks evolve.

"One line card today typically supports 20 Gb/s," says Applied Micro senior product marketing manager David Yeh. "But in their push to deploy a 100 Gb network, Verizon, for example, is looking for 120 Gb on a card."

They are not going to find it by simply ganging 10 Gbit Phy and framer/mapper chips, Yeh warns, because space and power constraints make this approach infeasible, even if it could be cost-effective. Even FPGAs, which seem like the obvious solution when the network is in transition, have their issues at these speeds. In principle, the latest 40nm FPGAs can handle 100 Gb throughput. But in practice, Yeh says, it is proving very difficult to get all the high-speed serial I/O and all of the gates for a 100 Gb line card on a single device. And two high-end FPGAs begin to present real cost and power issues.

Needless to say, Applied Micro has a solution to offer. The company has in effect integrated six of its Pemaquid 10 Gb Phy/framer/mapper chips onto a single 40nm device, called the PQx family. The design is approaching tape-out, and Applied Micro Transport Business Unit general manager Sandeep Gupta confidently expects to start sampling in July.

The PQx family will have two members, the PQ60 and PQ50, apparently based on the same die but with different testing. The PQ60 uses its six 10 Gb I/Os as independent ports, with SONET jitter compliance, for glueless attachment to six XFP or SFP+ optical modules. It is aimed at Carrier Ethernet applications. The PQ50 uses the same I/O ports to attach gluelessly to a 40 Gb CFP module through a single XLAUI or OTL3.4 port. There is also a 24-lane SFI5.1 port for connection to MSA 300 modules. Gupta says the PQ50 targets transponders, muxponders, and ROADMs in the telecom space. On the system side, the chip offers six XAUI/RXAUI ports or a 12-lane Interlaken port as configuration options for attaching to NPUs, switch fabrics, or external Ethernet MACs.

Internally, the chip contains the blocks needed for Layer 1/2 functionality, including the necessary mapping modes for OTN, multi-10Gb and 40 Gb MAC/PCS termination, and FEC hardware. The data sheet states that the PQ60 is functionally equivalent to six Pemaquid chips plus added support for UFEC forward error correction.

This integration was no small task, according to Gupta and Yeh. The die must support six 10 Gb serial interfaces to SONET standards, plus 24 lanes at up to 6.25 Gb each for the system interface, plus a 16-bit microprocessor bus, all running concurrently with over 100 million gates of logic.

"This scale of integration not only stressed our internal architecture, but our tool chain as well," Gupta says. Along with managing the sheer size of the project, the Applied Micro team had to apply special measures for digital noise control, and to develop new, very-low-power I/O cells and a novel approach to leakage control. Far more than a simple integration of six instances of an existing chip, the PQx represents a reimplementation at a new process node, under entirely new power- and noise-control regimes. Such is the cost of staying in touch with connectivity providers’ needs.