Instruments-on-chips idea enters FPGA land

DAFCA, the company that some time ago introduced reconfigurable instruments embedded in SoC designs, is moving to simplify their user interface and reduce license fees in a bid to expand their reach. And, recognizing the growing importance of FPGAs both as verification vehicles and as targets for SoC designs, the company has explicitly included FPGAs in its list of capabilities. These moves are embodied in two new products the company announced this morning.

DAFCA licenses tools and IP with which you can embed digital instruments in your chip design. The tools then allow you to configure those instruments, tie them together, and perform measurements while the chip is running. The underlying technology is a digital-CMOS-compatible FPGA fabric which the DAFCA tools sprinkle around in small patches throughout the design. Once the chip is up and running, measurement tools configure the FPGA blocks into logic-analyzer-like instruments, connect them to signals from the chip, and direct them to perform measurements.

The fabric can implement any combination of three functions: a watch point, a control point, or a transaction engine. The first two are probably self-explanatory to logic-analyzer users. The transaction engines employ both watch and control points to perform transactions between the DAFCA instruments and the functional logic of the chip.

DAFCA CTO Paul Bradley says that the tools and IP, originally intended to be an aid during silicon bring-up, have found a number of other applications. In addition to debugging silicon on the bench, he says, customers have used the instruments to assist in software debug, in real-time assertion-checking while the chip is running, and in accelerating manufacturing test.

With all this usefulness, the ClearBlue product, as DAFCA calls its offering, appears to have a lot of benefits. But it also has one of the disadvantages often seen in the initial release of a new kind of EDA tool: complexity. In their enthusiasm to make all the capabilities of the ClearBlue concept available to advanced customers, the DAFCA designers created a user interface that may have been a little intimidating to first-time users.

DAFCA’s first new product announcement today addresses that issue. The company is offering a restricted set of the full ClearBlue capabilities with a much-simplified user interface. ClearBlue Express limits the number of signals the system can watch to 1K. It allows only one transaction engine on the chip. And it does not support control or stimulus of the chip from the ClearBlue fabric. In effect, Express implements a sophisticated passive logic analyzer, without pattern-generator capabilities. In exchange for these limitations, the package offers a simple, five-screen GUI, and a low price, starting at $15K.

The second product stems from an interesting point about the way the DAFCA tools work, and a new market opportunity. "We realized," Bradley said, "that since the actual configuration of the instruments was done in standard RTL, customers could just as easily use the instruments during RTL simulation, or for that matter in an FPGA." This last part is important for two reasons. The first, Bradley points out, is that most design teams now use FPGAs as logic verification vehicles. And so the ClearBlue tools become an ideal test bench for the FPGA: generating on-chip instrumentation, operating the instruments, and organizing the resulting data. And the same instruments that ClearBlue puts into the FPGA can be inserted into the chip design as well, to be embedded in the final IC. In this way the FPGA verification vehicle and the final chip will have the same test bench.

To expedite this use of the tool, DAFCA is announcing the second product: ClearBlue FPGA. This product also offers the simplified five-screen GUI—but with expanded options on each screen–and it offers a low $7,500 per seat license fee. But as the name implies, this version is intended specifically for FPGA-based debug and verification. ClearBlue FPGA is does not have Express’s limitations on input signals or on the number of transaction engines, and it does allow stimulus and control of the FPGA design.

Another novel feature of the FPGA version is that it supports prototypes that require more than one FPGA chip. Using the same FIFO interface that original ClearBlue uses to pass information across clock boundaries, ClearBlue FPGA can pass data and triggers between FPGA chips, allowing cross-triggering, or examination of state that is not confined to just one chip. Such interchip links cannot be instantaneous, of course, so the user has the added complexity of understanding the interchip latency.

As a final note, Bradley suggested that this would not be the last specialized application DAFCA would investigate for ClearBlue. Beyond FPGA prototypes, software development, and even FPGAs in manufacturing, DAFCA is watching another area: security. The ability of ClearBlue to put transparent, real-time instruments into the end-silicon is not just useful for assertion-checking for real-time error recovery. It can also be applied to user authentication, counterfeit detection, and intrusion or tamper detection. Given that all these issues are growing problems for semiconductor vendors and their customers, this could turn out to be a whole new application area for instruments-on-chip.