180nm: with apologies to Oldsmobile, it's not your father's process

As much time as we spend here discussing the challenges of 40nm or the promises of 28nm, 180 must look like a typo. But in fact two announcements this week clearly show that 180nm processes are alive and well, albeit today as niche offerings rather than mainstream SoC processes. For some designers, 180 is still a geometry to migrate to, not a legacy to migrate from.

There are several possible reasons for looking at 180nm. Maybe the most obvious is that the technology is mature, the equipment is likely to be fully depreciated, and hence the wafers are likely to be cheap. And the mature tools will be affordable as well. If you are doing a moderate-sized design—say, no more than a few million gates—180 may be close to optimum die cost.

Another important reason is precision analog circuitry. A 180nm process, with its 1.8V core supply and 3.3V native I/O, lets you work with a much larger dynamic range. Large transistors and passives are sitting on much less expensive real estate than they would be at, say, 40nm. Process variations–especially in device-matching situations–and leakage currents are almost negligible most of the time, so you can use classical circuit topologies and still expect excellent yields. Models are mature and accurate. But at the same time the logic-gate density is high enough to allow substantial digital blocks on the die.

One proof of this concept was the announcement yesterday of a new 180nm mixed-signal process from ON Semiconductor. Running on the 8-inch line in Gresham Oregon that ON acquired from LSI Logic, the process offers up to 124K gates/mm²; resistors and stackable MIM capacitors; a wide range of analog, digital, and I/O libraries and memory options. In other words, it’s just the sort of process you would look for if you had an analog/mixed-signal design in 350nm and needed to integrate a CPU and some major logic blocks. ON adds, rather cryptically, that there is a "high voltage roadmap" for the process.

That last statement may be a veiled reference to the challenge ON faces from another new 180nm process, this one being jointly developed by IBM and austriamicrosystems. The process combines an IBM RF/CMOS formula with a high-voltage module from austriamicrosystems, and its PDK is supposed to be out fairly soon. It is relevant here because it is the target process for the second announcement I mentioned, an entry into the commercial IP market by design-services company asicNorth.

asicNorth’s first foray into off-the-shelf IP will comprise two A/D converters: a 12-bit, 125 Msample/s pipelined design aimed at the usual communications, GPS receiver, and medical markets, and a 10-bit, 2 Msample/s successive-approximation converter aimed at the low-power, small-footprint market.

The company says the latter part offers excellent performance for the power and area. The fast part, on the other hand, has, as you would expect, an appetite: 250 mW at full performance. To adapt it to power-sensitive markets, asicNorth has come up with an interesting power-throttling approach to energy savings. If you can get by with less performance, you can turn down the applied voltage on the V_bias pin and save power. Both converters, by the way, can float their inputs up to the maximum range of the process, which is somewhere around 100V, so you can get the full 1.8V input swing at a very high offset.

asicNorth has taped out both blocks and is awaiting silicon. (When you are a Certified Ready-for-IBM member, you apparently get some early access.) The company intends both to offer the blocks as off-the-shelf IP, and also to use them as reference designs that can serve as the basis for further customization.

So 180 is alive and well and living in moderate-scale, mixed-signal land. It’s not a process anyone is likely to revert to as a money-saving strategy on a 65nm SoC. But as a way to integrate significant amounts of digital functionality with precision analog and high-voltage circuits, the node still shines.