Virage Logic pushes into DDR3 territory with full interface IP

As DDR3 moves closer to widespread deployment, the JEDEC standard is creating a problem for SoC designers—yet another extremely challenging high-speed serial interface to implement. Not only is DDR3 a challenging protocol with signaling at very high frequencies, but at these frequencies the interactions between decisions in the SoC design team and choices—or simple lack of expertise—on the part of the package and board designers can be catastrophic. At 1.6 Gbits/s a non-functioning memory channel is almost the default case.

Virage Logic is announcing their approach to the problem today with a new set of interrelated IPs that together form a tool kit for implementing DDR3 interface designs, addressing what the company sees as the primary risks in this standard. The offering comprises a modular DRAM controller, a unique digital PHY, and a set of tunable I/O cells. The entire interface is digital right up to the I/O ring.

In some ways, the controller block is the crown jewel of the set. Virage claims that their controller has the highest throughput of any currently available third-party DRAM controller. "It has even benchmarked well against any customer’s proprietary controller we have compared it to," claims Kamalesh Ruparel, Virage VP and GM for application-specific IP.

The controller is a single-port device with a modular design, so users can include only as much smarts—and die area and power—as they need. Available features include out-of-order execution and quality-of-service provisions in a CAM-based internal architecture. Virage says that the high efficiency of the block allows the careful SoC designer to achieve very high channel utilization, which in practice often means the channel can operate at a lower frequency, making things much easier for downstream partners such as package vendors, board designers, and board fabricators.

The PHY is similarly designed for relative ease of use. All ease is relative as you approach 1.6 Gbits/s, one supposes. Unlike the majority of PHY designs in this space, Virage’s uses a digital delay-locked loop as its basic timing generator, rather than the conventional analog phase-locked loop. The DLL is designed to be implemented with standard-cell elements rather than a custom circuit, so there is essentially no custom circuit design involved in implementing the PHY in a new SoC.

That doesn’t make it trivial, Ruparel warns. Virage will work with customers to verify the design, selecting the correct digital cells for the PHY block, SPICEing the critical DLL, and then providing the result as a hard macro to the SoC team. This does mean that the majority of the hard work falls on Virage, not the customer. "There are power-quality requirements, route-over guidelines and the like," said product line manager Luigi Ternullo, "but nothing out of the ordinary. Even the need for analog isolation is minimal because of the digital design."

Virage sees the I/O cells as an equally critical component of a successful, robust design. The JEDEC DDR3 standard specifies a fair amount of adaptability in the I/O ring. To this, Virage has added dynamic tuning adjustments, controls for duty cycle, drive strength, slew rate, driver pre-emphasis, and dynamic power management. All of this is necessary flexibility to adapt to the surprises that package choices, board design, and board fabrication variations can throw at the interface. But the cells can get fairly complex to tune, as the various knobs interact. So Virage provides extensive guidelines for the users. The company will also consult with designers who want to use their own I/O cells.

The DDR3 interface IP is available for design-ins as of today, Virage says. But at the moment it is still a work in progress. Virage expects to have a full silicon validation report on the IP in October, after it has received its test chips. One customer, already working with Virage on a design-in, expects to tape-out a real chip design in December, according to the company.