Adaptive circuitry defines scaling for ISSCC keynoters

Plenary-session keynotes at the International Solid State Circuits Conference today included two forward-looking papers—one by Hitachi fellow Kiyoo Itoh and one by Intel senior fellow Mark Bohr—both dealing with the question of what scaling means in the era beyond 90 nm. Bohr’s paper was the more general of the two, treating the whole question of how we will continue to get benefits out of moving to the next smaller process. Itoh’s paper was the more specific, addressing voltage scaling in particular.

Bohr began with the usual recitation of the steps Intel has taken so far to continue process scaling: introducing strain engineering at 90 nm and a high-k/metal-gate process at 45 nm. After citing some of the company’s specs for its 45 nm process, he moved on to what we could expect for 32 nm.

At this node, Bohr said, there will be no more major changes in the recipe. Intel will start (finally) using immersion lithography on critical layers, but will continue with the sort of strain engineered, high-k/metal-gate process it now uses. The combination of immersion and these tools, Bohr said, would give Intel sufficient image fidelity on the critical transistor shapes to achieve a 112.5 nm contacted gate pitch, a 0.171 micrometer² bit cell, and 1.6/1.3 mA/micrometer drive current for N and P FETs, respectively.

But these advancements by themselves would not be sufficient for end-users to see all the value of the new process, Bohr implied. Coming with the process changes would be an evolution that is gradually turning the microprocessor into a self-regulating SoC. Bohr, using Nehalem as an example, cited the use of low-resistance, low-leakage power-gating transistors to turn on and off whole CPU cores or blocks of SRAM, and adaptive PLLs that can quickly change frequency to adapt to shifts in supply voltage. The latter technique by itself can increase clock frequency by 5 percent compared to worst-case design techniques, he claimed.

Bohr continued that Nehalem has an on-chip power controller block based on a proprietary microcontroller and a network of sensors strung throughout the chip. Under firmware control the block can keep the circuitry in Nehalem operating within its safe limits, shut down blocks that are not in use, and increase the frequency of active blocks when other blocks are quiescent—for example turning up the clock on one CPU when several others are powered-down.

In his talk Itoh explored the notion of using adaptive circuits at the transistor, rather than the block, level to allow reduced operating voltage. Itoh pointed out that a number of scaling limitations–including among others the inability to reduce threshold voltage in MOSFETs, the increasing difficulty of controlling threshold-voltage variation, and increasing uncertainties in the actual voltage delivered to circuits for a given supply voltage–were making it very difficult for advanced ICs to operate at less than 1V. As things stand, he said, this problem will get worse rather than better with process scaling, and could even force operating voltages to rise in future generations.

Itoh discussed the advantages of finFETs at lower voltages, and then launched into a discussion of gate-level adaptive circuits to manage threshold variation on the fly. His technique is based on the observation that the standard deviation of the distribution of threshold voltage goes down as the highest necessary threshold voltage in a circuit goes down. And as the distribution gets tighter, the circuit can operate on a supply voltage closer to the threshold voltage.

Itoh described circuits in which gate-source back-bias reduced the threshold voltage on individual transistors to zero–while still suppressing leakage–when the devices were inactive. This in turn allows use of a lower supply voltage on those circuits. When applied across an entire logic block, the effect is a net reduction variation in threshold voltage, and hence in the minimum supply voltage necessary to operate the block reliably. By this technique, Itoh suggested, finFET circuits including moderate-speed logic, DRAM, and some SRAM could operate reliably at 0.5 V.

The two very different approaches to adaptive cirtuits—one coarse-grained and slow to change, and one working on a transistor level—illustrate the range of ideas designers are exploring in their attempt to overcome the limitations that power, temperature, and variations are imposing on further scaling. One suspects this is just the beginning of the story.