Mentor adds SystemC support to Catapult C

Mentor Graphics, which probably leads the market for HLL synthesis, has continued to expand the reach of its product while sticking with the core Catapult C synthesis engine. In December the company added support for control-logic synthesis and some level of power management. Today, Mentor took another step, adding a preprocessor to masticate SystemC code into a form useable by the Catapult C engine.

One of the challenges here is definition. SystemC usage covers a lot of space. For some people, SystemC is a way of documenting and exploring systems, generally at the transaction level. For a minority, it’s a cycle-accurate tool for creating test benches. For still others, it’s the first stage in synthesizing an actual design. Each of these users partakes of a different subset of the language, and uses their code in a different way. So a synthesis tool has to decide whom it is serving.

To some degree, Mentor is trying to please almost everyone. Product line director Shawn McCloud says the Mentor tool will handle abstract untimed C++ code, TLM 2.0-compliant SystemC, and cycle-accurate SystemC employing, for example, the wait construct.

A particular emphasis of Mentor’s effort, McCloud says, has been accurate representation and synthesis of complex bus interfaces and, in some instances, on-chip interconnect. The ability to generate production-quality RTL from SystemC representations of these structures, coupled with Catapult C’s existing ability to generate useful RTL for functional blocks, brings the tool closer to the ideal of digital full-chip synthesis.

With SystemC a good part of the point has always been test benches. And a good part of Mentor’s brand is verification. Accordingly, Mentor provides SystemC creation and simulation in Vista, including lint, coverage, and run-time-checking tools. After synthesis, your RTL has insertions generated by Catapult to assist in Questa RTL debug. And you can synthesize much of your SystemC test bench and reuse it at RTL as well.

Incrementally, HLL synthesis tools are addressing the full range of needs of a design team, both at the block level and at the full-chip level. But even as HLL tools improve, the design community continues to increase its reliance on IP blocks and IP integration methodologies. How often a full-chip design actually begins with an HLL representation and progresses linearly to tape-out is another question. It may be in the long run that the importance of these tools will lie in their ability to describe, model, and refine an assembly of IP, and to generate the necessary glue to hold the blocks together, rather than their niftiness at creating a chip from a clean sheet of paper. Time will tell.