A short look into the SoC future

One of the more offbeat panels at DesignCon last week brought together a group of industry luminaries—the technical people, not the CEOs—to discuss the future of the industry. Instead of nesting in the usual homilies about increasing disaggregation, increasing productivity, and the return of double-digit growth, this group actually came up with some useful gems of information.

The trend was led off by the always refreshingly candid Bryan Lewis, DataQuest chief analyst. He set the stage for further discussion with some hard realities: industry growth is going to be in single-digits, while the costs of a new SoC design, of a process development, and of fab construction are continuing to increase exponentially. Further, one of the few levers we might have had over design cost, hardware/software codesign, has not taken off, allowing software development costs to spiral right along with hardware ones.

With that cheery start, Ted Vucurevich, CTO for advanced R&D at Cadence, offered a good-news/bad-news couplet. On the good side, it appears that silicon active devices may continue to be viable until they run into a physical limit on heat transfer at about 1 nm. The bad news is that it is beginning to look like conventional interconnect, even with desperate measures such as air-gap isolation, may not scale beyond about 6 nm. Still, that’s a lot of headroom for an industry that is still centered somewhere around 90 nm.

Several speakers then took up the twin questions of SoC architecture and system development tools. The consensus, as summarized by ARM’s Tom Lantzsch, seems to be that architectures will continue to evolve toward multiple heterogeneous cores. These will be programmable early in an application’s life cycle, becoming more fixed-function as the application matures. No great surprise there. But the question of programming these things proved more interesting.

“The nirvana is a hardware abstraction layer,” offered AMD guru Mike Uhler. “Really, an instruction set architecture is a lousy API.” Uhler warned that this was a serious challenge, however. “I don’t think we can get there just by having our compilers do vectorization.”

Mathworks’ expert Giovanni Mancini added to this perspective, saying that the focus had to shift from details of the SoC design to functional correctness. “We need to work at the level of system models, and learn to see the design from the viewpoint of the customer’s experience with it,” Mancini said. “When system designers have to understand the details of the SoC, the SoC is too complex.”

But Mobashar Yazdani, who has of late become something of a go-to guy for bringing the hard reality of customer perspective to panels, was there with his customary note of caution, based on hard-won experience at Hewlett Packard. He warned that despite the need for design reuse, IP in fact continues to lag behind the needs of design teams, forcing additional design effort to bring supposedly functioning blocks into a new design. Further, he suggested, the option of continuing to march down the geometry path to salvation was becoming far more difficult. “At any given time there is a sweet spot,” he said, “and if you go above that, yield problems kill you. It’s often better to do a multi-die design at the sweet spot than to try to push integration by using a more advanced process.” Yazdani also offered a note of caution about one of the fundamental tools of our increasingly disaggregated industry. “You have to partner with other people,” he said, “but partnering has not proved to be as easy as it looks. It has its own problems.”

Taken together, we see an industry with slow growth, shrinking margins, spiraling costs, and a significant lack of tools that would allow us to break through any of these negative trends. Perhaps it’s not the most reassuring picture to be facing at the leading edge of a global recession.