Consortium rallies IP vendors behind SoI

The Silicon-on-Insulator Consortium (SOIC) has for several years been committed to the often thankless job of evangelizing the virtues of SoI to the fabless community. Of course this cause is of direct benefit to a few of the key members, such as wafer-blank manufacturer Soitec, foundry IBM, and heavy user AMD. But like all good evangelical movements, SOIC is blessed with genuine believers: senior industry figures who have experienced the benefits of SoI and want to share them.

Initially, the group’s focus was simply on demonstrating that there really are benefits, in terms of both speed and power. This done, SOIC turned to the more formidable task of proving that these benefits were achievable, by ordinary design teams using off-the-shelf tool flows on ordinary schedules. Member ARM took a big step in this direction last year by demonstrating that a design team without SoI experience, special tools, or unusual skill sets could do a cell-based ARM 1176 in SoI on schedule and with excellent results.

That leaves one big question: where does the IP come from? If you were ARM, with your own IP divisions, or an IBM ASIC customer, with access to IBM’s enormous libraries and porting skills, no problem. But for the rest of us, the answer to this question has sounded distinctly unreassuring.

That has now changed. This morning SOIC announced the IP Ecosystem Program. As the name suggests, the program brings together a wide variety of SoI-proven, synthesizable and hard IP so you can find it, evaluate it, and license it for use in a COT design. Future expansion plans will bring not just more IP, but EDA vendors and design services providers into the program as well, giving strength to the word ecosystem in the title.

The initial members of the program are pretty much of the IP persuasion. They include ARM, IBM, and Cadence. Synopsys and Boeing have just joined, and will be contributing IP too. If Boeing sounds like the odd name in this list, we are talking here about a group within Boeing that has a considerable library of 45nm SoI IP to offer. So far, the collection includes cell libraries—both digital and mixed-signal–and key physical blocks such as PLLs from ARM; and memory compilers for register files, SRAM, ROM, and even TCAM, along with Serdes and other important pieces from IBM. Much of the IBM IP has previously only been available to ASIC customers, according to IBM Common Platform marketing manager Duncan Needler. Cadence is also adding IP, apparently including some of their interface blocks.

As of now, the IP is only for IBM’s 45nm SoI foundry process. But SOIC executive director Horacio Mendez said the process choices would be expanding, back to 65nm and forward to 32nm. Mendez didn’t say so, but presumably other foundries’ processes will be added as well, since GlobalFoundries, Samsung, ST, and UMC are all members of the larger consortium.

The collection is foundational, but it is not primitive. For example, the high-speed serial entries include not just PLLs and SerDes, but the DDR delay line critical to timing of a DDR interface, Needler said. The intent is to provide full interface kits, not just a random collection of pieces. Another point worth mentioning is that IBM is offering its crown-jewel embedded DRAM to the program, with a separate negotiation that is rather more extensive than a simple IP license. This may be the first time IBM has offered the trench eDRAM outside an ASIC agreement.

If there is an obvious piece missing from the IP list so far, it would be ARM processor cores. ARM vice president of marketing for physical IP John Heinlein said that while ARM is not offering SoI-proven cores through the program, it is offering SoI-proven libraries. "And today most ARM cores are synthesized, not licensed in physical form," Heinlein observed.

All the program’s IP has been loaded into Cadence’s Chip Estimate IC planning tool, so users can browse the offerings, compare them, and assemble a set of IP in order to estimate the final chip’s power, area, and performance. Negotiating license agreements with the individual vendors is still up to the design team, however. There is no intent to provide one-stop licensing through the program.

If it accomplishes nothing else, the IP Ecosystem Program will give architects and design managers a way to estimate what SoI could do for their project, and to quantify just how much new design work would be involved. This all by itself would be a major step forward for those not-infrequent designs that probably should be using SoI, but have believed it too difficult, too risky, or simply too ill-defined a choice.