Heard at the GSA IP Conference: do you really need silicon validation for IP?

One of the more interesting panels at the GSA IP Conference last week asked the question of whether it is really necessary for IP vendors to continue providing silicon test chips to validate their IP. Under the watchful eye of moderator and Cadence group director Nitin Deo, what might sound like a no-brainer question in fact produced some very thoughtful discussion. Deo opened the panel with a simple question: "Silicon validation has become a monumental task for IP vendors. Is it really necessary?"

The first response was from Robert Heaton, director of analog solutions architecture at MIPS Technologies. "Just about every major piece of IP is now analog or mixed-signal in some way," Heaton said. "And one of the big problems is that hardware design languages misrepresent analog/mixed-signal (AMS) circuits. So there are always basic questions about whether the IP you are looking at is actually a fit for your application.

"You could look for certified IP," Heaton continued. "But certification takes time. So ‘certified’ virtually means ‘out of date.’ If you are working on the leading edge, you can’t expect to have everything come out right on the first pass. Working, maybe, but not fully correct. If you can wait to use mature IP; and if you have a good flow, you have some paranoia, and some luck, you might get first-time-right. Ideally, you would like to have a silicon test chip yourself, that you could surround with FPGAs to provide a context like the one the IP will have in your design."

Ming Hsu, vice president of world-wide support at UMC, tended to agree with the pessimism. "We find that silicon validation is necessary, but not sufficient," he stated. "Silicon validation is a negative confirmation: it proves that the performance is not too low, the functionality is not obviously wrong, and the initial reliability is not low. But it’s no guarantee. Ideally, you would also like validation to address yield, sensitivity to variations, and the valid process windows."

Kamalesh Ruparel, VP & GM for ASIC solutions at Virage Logic, agreed. "Silicon validation misses the point," he claimed. "It’s a mania. It’s too narrow an idea to deal with the problem." Ruparel went on to describe three types of validation he considered necessary. "You need silicon validation for the analog portions of a design," he listed. "In addition, you need functional verification for the digital portions. But further, you need system-level verification for the high-speed interface IP—for the signals that cross package boundaries. Ordinary silicon validation cannot replace either functional or system validation."

Heaton followed up on this idea. "Something like a CPU is actually a relatively easy validation problem, because it is very constrained. For something like a PLL, on the other hand, you have to model the IP’s intended surroundings, or the validation means nothing. AMS validation is so complex that in reality it is based in the culture of the design team, not in their tool chain. There are still some very basic problems here. For instance, the industry still has no universally-accepted definition of jitter that would allow it to compare validation results."

Ruparel offered a stronger criticism. "When you look at what’s happening with advanced processes, this industry is falling apart. The big customers can demand and get adequate validation data. But the middle customers and the little guys basically don’t get validated IP for leading-edge processes. Often these customers don’t know exactly what to ask for, and they get into trouble."

Wayne Dai, CEO of design house VeriSilicon, agreed that much can go wrong. "We see documentation errors, and we see design teams misinterpreting the information the IP designers give them. But often, we simply see problems emerge when the chip team attempts to use the IP in a new context that the IP team didn’t anticipate. These things happen, but we believe more validation can still avert non-working silicon."