Statistical timing analysis may understate the problem of timing variations

At the Design Automation & Test Europe (DATE) last week, IMEC reported on some fascinating work on percolating process variation data back up the design chain to the level of extraction and Verilog netlists. But the European research consortium also reported some results that could be profoundly unsettling for designers who are relying on statistical timing analysis: assumptions in the technique could be wrong, and the way we validate models with silicon could be hiding incorrect results.

The discrepancies appeared because the IMEC research uses a method of propagating variations—weighted Monte Carlo simulation—that does not make assumptions about the statistical distribution of the variations. IMEC’s results on 45 nm circuits predicted significantly larger ranges of delays than did conventional statistical tools. Unfortunately, IMEC’s results matched the silicon.

Part of the problem, according to IMEC senior scientist Miguel Miranda-Corbalan, is that as you move back up the chain from, say, metal-thickness variations to timing variations, the influence of outliers is far greater than the models in conventional tools would predict. “Traditional analysis looks at the critical paths, and predicts the influence of variation on those paths to predict the overall impact on the circuit’s timing,” Miranda said. “But this ignores the fact that variations can create new critical paths, which then govern circuit performance. Outlier values have far wider influence than just the paths that traditional tools normally examine.”

There is a second problem as well. Existing static timing tools, in order to describe the statistical variation in a parameter in a compact form, assume a symmetrical Gaussian distribution. Unfortunately, the IMEC work indicates, by the time you have transformed process variations all the way back to timing variations, the distributions are not Gaussian, and not even approximately symmetrical. Some are extremely skewed toward the slow end of the distribution. This is primarily because of transistor degradation over time, which pulls failing transistors away from the distribution.

This violation of the assumptions leads the statistical analysis tools to provide confidence intervals that are far too optimistic. The real distribution of timing variations is not always symmetric around the invariant case, said IMEC activity leader Bart Dierickx. In fact, a significant part of the distribution may lie outside the PVT corners. Many of the original critical path delays may continue to be symmetrical around the typical-typical corner, but “the overall delay is determined by the worst path, not the average critical path,” the manager pointed out. One particular test chip was supposed to show a 2x improvement in speed moving from one process generation to the next, but in fact showed a 20 percent improvement, to give an idea of the scale of the problem.

So why has this not been widely reported? One answer may be that the industry relies on ring oscillators to gauge the delay variations in a new process. This is an unfortunate choice, because ring-oscillator test chips contain large numbers of identical simple structures, and therefore almost by construction comply with the assumption of Gaussian distributions of timing variations. So conventional statistical methods are ideal for predicting the behavior of ring oscillators. But the same is not true of circuits that contain a rich combination of structures—IMEC’s results warn that conventional statistical tools may not predict these well at all.